Patents Assigned to Invensas Corporation
  • Publication number: 20190341350
    Abstract: Dielets on flexible and stretchable packaging for microelectronics are provided. Configurations of flexible, stretchable, and twistable microelectronic packages are achieved by rendering chip layouts, including processors and memories, in distributed collections of dielets implemented on flexible and/or stretchable media. High-density communication between the dielets is achieved with various direct-bonding or hybrid bonding techniques that achieve high conductor count and very fine pitch on flexible substrates. An example process uses high-density interconnects direct-bonded or hybrid bonded between standard interfaces of dielets to create a flexible microelectronics package. In another example, a process uses high-density interconnections direct-bonded between native interconnects of the dielets to create the flexible microelectronics packages, without the standard interfaces.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Applicant: Invensas Corporation
    Inventors: Shaowu Huang, Javier A. Delacruz
  • Publication number: 20190341361
    Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Applicant: Invensas Corporation
    Inventors: Liang Wang, Ilyas Mohammed, Masud Beroz
  • Patent number: 10468380
    Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 5, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kyong-Mo Bang
  • Patent number: 10460958
    Abstract: Microelectronic assemblies and methods of making the same are disclosed.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: October 29, 2019
    Assignee: Invensas Corporation
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Patent number: 10446441
    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 15, 2019
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10446456
    Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 15, 2019
    Assignee: Invensas Corporation
    Inventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram
  • Patent number: 10440822
    Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130?) covered by a conductive coating (130?) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: October 8, 2019
    Assignee: Invensas Corporation
    Inventors: Bong-Sub Lee, Cyprian Emeka Uzoh, Charles G. Woychik, Liang Wang, Laura Wills Mirkarimi, Arkalgud R. Sitaram
  • Publication number: 20190304904
    Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Applicant: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Zhuowen Sun
  • Patent number: 10431648
    Abstract: Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 1, 2019
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Hong Shen, Rajesh Katkar
  • Patent number: 10418338
    Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: September 17, 2019
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10409677
    Abstract: The invention pertains to semiconductor memories, and more particularly to enhancing the reliability of stacked memory devices. Apparatuses and methods are described for implementing RAID-style error correction to increase the reliability of the stacked memory devices.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 10, 2019
    Assignee: Invensas Corporation
    Inventor: William C. Plants
  • Patent number: 10410977
    Abstract: A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: September 10, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar
  • Publication number: 20190272802
    Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
    Type: Application
    Filed: March 5, 2019
    Publication date: September 5, 2019
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar
  • Publication number: 20190273016
    Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.
    Type: Application
    Filed: September 20, 2018
    Publication date: September 5, 2019
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Gabriel Z. Guevara, Min Tao
  • Patent number: 10403577
    Abstract: Dielets on flexible and stretchable packaging for microelectronics are provided. Configurations of flexible, stretchable, and twistable microelectronic packages are achieved by rendering chip layouts, including processors and memories, in distributed collections of dielets implemented on flexible and/or stretchable media. High-density communication between the dielets is achieved with various direct-bonding or hybrid bonding techniques that achieve high conductor count and very fine pitch on flexible substrates. An example process uses high-density interconnects direct-bonded or hybrid bonded between standard interfaces of dielets to create a flexible microelectronics package. In another example, a process uses high-density interconnections direct-bonded between native interconnects of the dielets to create the flexible microelectronics packages, without the standard interfaces.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Invensas Corporation
    Inventors: Shaowu Huang, Javier A. Delacruz
  • Patent number: 10403599
    Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide improved signal transmission of 1-2 GHz up to 20-60 GHz bandwidth for each 15 mm length, for example. The embedded organic interposers are not limited to use with memory modules.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Patent number: 10403510
    Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: September 3, 2019
    Assignee: Invensas Corporation
    Inventors: Andrew Cao, Michael Newman
  • Patent number: 10396114
    Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: August 27, 2019
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Michael Newman, Terrence Caskey
  • Patent number: 10396041
    Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.
    Type: Grant
    Filed: March 5, 2017
    Date of Patent: August 27, 2019
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Ilyas Mohammed, Masud Beroz
  • Patent number: 10381326
    Abstract: A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: August 13, 2019
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Arkalgud R. Sitaram, Andrew Cao, Bong-Sub Lee