Patents Assigned to Invensas Corporation
  • Patent number: 10854578
    Abstract: Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 1, 2020
    Assignee: Invensas Corporation
    Inventor: Stephen Morein
  • Patent number: 10849240
    Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 24, 2020
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Hong Shen, Cyprian Emeka Uzoh
  • Patent number: 10847562
    Abstract: An image sensor device, as well as methods therefor, is disclosed. This image sensor device includes a substrate having bond pads. The substrate has a through substrate channel defined therein extending between a front side surface and a back side surface thereof. The front side surface is associated with an optically-activatable surface. The bond pads are located at or proximal to the front side surface aligned for access via the through substrate channel. Wire bond wires are bonded to the bond pads at first ends thereof extending away from the bond pads with second ends of the wire bond wires located outside of an opening of the channel at the back side surface. A molding layer is disposed along the back side surface and in the through substrate channel. A redistribution layer is in contact with the molding layer and interconnected to the second ends of the wire bond wires.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 24, 2020
    Assignee: Invensas Corporation
    Inventor: Rajesh Katkar
  • Patent number: 10840135
    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 17, 2020
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10818629
    Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 27, 2020
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar
  • Patent number: 10813214
    Abstract: A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: October 20, 2020
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Craig Mitchell, Belgacem Haba, Ilyas Mohammed
  • Patent number: 10811388
    Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 20, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Arkalgud R. Sitaram
  • Patent number: 10806036
    Abstract: In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 13, 2020
    Assignee: Invensas Corporation
    Inventors: Reynaldo Co, Grant Villavicencio, Wael Zohni
  • Patent number: 10802285
    Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 13, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar
  • Publication number: 20200312815
    Abstract: Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Applicant: Invensas Corporation
    Inventor: Stephen Morein
  • Patent number: 10790222
    Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 29, 2020
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal
  • Publication number: 20200279821
    Abstract: A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 ?m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 ?m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives.
    Type: Application
    Filed: January 29, 2020
    Publication date: September 3, 2020
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 10756049
    Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: August 25, 2020
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Patent number: 10750614
    Abstract: Deformable electrical contacts with conformable target pads for microelectronic assemblies and other applications are provided. A plurality of deformable electrical contacts on a first substrate may be joined to a plurality of conformable pads on a second substrate during die level or wafer level assembly of microelectronics, for example. Each deformable contact deforms to a degree that is related to the amount of joining pressure between the first substrate and the second substrate. The deformation process also wipes each respective conformable pad with the deformable electrical contact to create a fresh metal-to-metal contact for good conduction. Each conformable pad collapses as pressured by a compressible material to assume the approximate deformed shape of the electrical contact, providing a large conduction surface area, while also compensating for horizontal misalignment.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 18, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Gabriel Z. Guevara
  • Patent number: 10748858
    Abstract: High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 18, 2020
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Ilyas Mohammed, Masud Beroz
  • Patent number: 10748840
    Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: August 18, 2020
    Assignee: Invensas Corporation
    Inventor: Masamichi Ishihara
  • Publication number: 20200235085
    Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: Invensas Corporation
    Inventors: Min Tao, Liang Wang, Rajesh Katkar, Cyprian Emeka Uzoh
  • Publication number: 20200227360
    Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Applicant: Invensas Corporation
    Inventors: Shaowu Huang, Javier A. Delacruz
  • Publication number: 20200212013
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Patent number: 10700002
    Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: June 30, 2020
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Zhuowen Sun