Abstract: An address generator for use in conjunction with a fast Fourier transform processor includes an efficient architecture for computing the memory addresses of input data points, output data points and twiddle coefficients. In particular, multiplication operation in the calculation of memory addresses is minimized. Instead, a cascaded series of adders is used, in which the output of one adder is input to the next adder. At each stage of the cascaded adders, the same input variable is successively added. The cascaded adder structure is used in the writing address generator, the reading address generator and the twiddle coefficient address generator. In addition, a plurality of modulo N circuits is used in series with the cascaded series of adders to generate the twiddle coefficient addresses.

Abstract: The discrete Fourier transform (DFT) is computed in a plurality of parallel processors. A DFT of length N is divided into r partial DFTs of length (N/r), in which the r partial DFTs are calculated in separate parallel processors and then combined in a combination phase to form a complete DFT of length (N). The r partial FFTs are able to be computed in parallel multiprocessors by defining the mathematical model of the combination phase in such manner so as to allow the r parallel processors to operate independently and simultaneously. A second embodiment presents a radix-r fast Fourier algorithm that reduces the computational effort as measured by the number of multiplications and permits the N/r parallel processors to operate simultaneously and with a single instruction sequence.

Abstract: A Fast Fourier Transformation (FFT) method and apparatus is implemented using a radix-r butterfly design based on a reduced single phase of calculation, termed a butterfly-processing element (BPE). Butterfly calculations are each executed in the same number of iterations, and comprised of substantially identical butterfly-processing elements. The resulting algorithm, in which a number of parallel processors operate simultaneously by a single instruction sequence, reduces both the computational burden and the communication burden. The use of substantially identical butterfly-processing elements, repeated in combination to form a radix-r butterfly, enables the design of FFT butterflies containing identical structures and a systematic means of accessing the corresponding multiplier coefficients stored in memory. The butterfly-processing element substantially reduces the complexity of the radix-r butterfly, particularly for higher order radices.

Abstract: An active noise suppression system for use in noisy environments includes a dual microphone noise suppression system in which the echo between the two microphones is substantially canceled or suppressed. Noise is cancelled by the use of first and second line echo cancellers, which model the delay and transmission characteristics of the acoustic path between the two microphones. In a first embodiment, a noise suppression system acts as an ear protector, canceling substantially all or most of the noise striking the dual microphones of the ear set. In a second embodiment, a noise suppression system in accordance with the present invention acts a noise suppression communication system, suppressing background noise while allowing speech signals to be heard by the wearer.