Patents Assigned to Kabushika Kaisha Toshiba
  • Patent number: 11777025
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, first and second electrodes, a gate electrode, a gate terminal, a first conductive member, a first terminal, and a first insulating member. The semiconductor member includes first and second semiconductor regions, and a third semiconductor region provided between the first and second semiconductor regions. The first electrode is electrically connected to the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The gate terminal is electrically connected to the gate electrode. The first conductive member is electrically insulated from the first and second electrodes, and the gate electrode. The first terminal is electrically connected to the first conductive member.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: October 3, 2023
    Assignees: KABUSHIKA KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yusuke Kobayashi, Tatsunori Sakano, Hiro Gangi, Tomoaki Inokuchi, Takahiro Kato, Yusuke Hayashi, Ryohei Gejo, Tatsuya Nishiwaki
  • Patent number: 9059327
    Abstract: According to an embodiment, a nitride semiconductor Schottky diode includes a first layer including a first nitride semiconductor and a second layer provided on the first layer and including a second nitride semiconductor having a wider band gap than the first nitride semiconductor. The diode also includes an ohmic electrode provided on the second layer and a Schottky electrode provided on the second layer. The second layer includes a region containing an acceptor in the vicinity of the Schottky electrode between the Schottky electrode and the ohmic electrode.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 16, 2015
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Mayumi Morizuka
  • Patent number: 8416958
    Abstract: A signal processing apparatus is configured to change volume level or frequency characteristics of an input signal with a limited bandwidth in a first frequency range. The apparatus includes: an information extracting unit configured to extract second frequency characteristic information from a collection signal with a limited bandwidth in a second frequency range different from the first frequency range; a frequency characteristic information extending unit configured to estimate first frequency characteristic information from the second frequency characteristic information extracted by the information extracting unit, the first frequency characteristic information including the first frequency range; and a signal correcting unit configured to change volume level or frequency characteristics of the input signal according to the first frequency characteristic information obtained by the frequency characteristic information extending unit.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: April 9, 2013
    Assignee: Kabushika Kaisha Toshiba
    Inventors: Takashi Sudo, Masataka Osada
  • Patent number: 8394877
    Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc?No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: March 12, 2013
    Assignee: Kabushika Kaisha Toshiba
    Inventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
  • Publication number: 20070133174
    Abstract: According to one embodiment, an information processor includes a semiconductor device, a heat pipe and an insulated magnetic member. The semiconductor device is provided on a substrate, and emits electromagnetic radiation and heat during an operation thereof. The heat pipe includes a heat-receiving end and a heat-radiating end. The heat-receiving end is fixed to the semiconductor device to transmit the heat emitted from the semiconductor device. The heat-radiating end is separate from the semiconductor device. The magnetic member is mounted on the outer peripheral surface of the heat pipe between the heat-receiving end and the heat-radiating end.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 14, 2007
    Applicant: KABUSHIKA KAISHA TOSHIBA
    Inventors: Masashi Mikami, Heiwa Matsuoka, Yusuke Sugiura
  • Patent number: 7227228
    Abstract: An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. The silicon layer of the SOI device may include a channel region and source/drain regions. The SOI device may further include a gate insulator disposed on the channel region of the silicon layer, a gate disposed on the gate insulator and sidewall spacers formed a side surface of the gate. The dielectric film may also be disposed on an edge portion of the silicon layer. The device structure may further include metallization lines connecting through the isolation dielectric to the gate and to the source/drain regions.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: June 5, 2007
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Yusuke Kohyama
  • Patent number: 7139579
    Abstract: This invention relates to a wireless LAN access point including a communication unit capable of communication by the first wireless communication method, a unit which detects that the traffic density in the communication band used by the first wireless communication method exceeds a predetermined traffic density, and a unit which limits the traffic density in the communication band of the first wireless communication method by a wireless LAN client when the traffic density is detected to exceed the predetermined traffic density.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: November 21, 2006
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Ken Hatano
  • Patent number: 6539388
    Abstract: A data storage and retrieval system includes a data space area where a set of data belonging to a predetermined category and definition data describing definition of the structure and the presentation form of the data are stored, a data space retrieval section for retrieving data and definition data made to correspond to the data from the data space area, a data space operation section for rewriting the definition data made to correspond to the data retrieved by the retrieval section on the basis of another definition data stored in the data space area, and a display for displaying the data retrieved by the retrieval section on the basis of the definition data rewritten by the operation section.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: March 25, 2003
    Assignee: Kabushika Kaisha Toshiba
    Inventors: Masakazu Hattori, Mikito Iwamasa
  • Publication number: 20020045296
    Abstract: A method of manufacturing a semiconductor device according to this invention is characterized by including the steps of a) forming, on one major surface of a substrate, a gate structure constituted by either one of a dummy gate electrode and a gate electrode having an insulating film at least on bottom surface, and a device isolation insulating film so as to form a first groove divided by the dummy gate electrode or the gate electrode, to position the dummy gate electrode or the gate electrode in the first groove, and to form the gate structure to have an upper surface level not higher than an upper level of the device isolation insulating film, and b) forming source and drain electrodes in the first groove.
    Type: Application
    Filed: December 21, 2001
    Publication date: April 18, 2002
    Applicant: Kabushika Kaisha Toshiba
    Inventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
  • Patent number: 6339232
    Abstract: There is provided a semiconductor device in which gate electrodes of both an n-channel field effect transistor and a p-channel field effect transistor constituting a complementary field effect transistor are made of the same material and threshold voltages of both are sufficiently lowered. In the semiconductor device including an n-channel MOSFET and a p-channel MOSFET which constitute a CMOS structure, the gate electrode of the n-channel MOSFET and the gate electrode of the p-channel MOSFET are made of the same material, at least a part of a channel region of the n-channel MOSFET is formed in a strained Si layer, at least a part of a channel region of the p-channel MOSFET is formed in an SiGe layer, the work function of the material making the gate electrodes is higher than an energy difference between the conduction band edge of the strained Si layer and the vacuum level, and is lower than an energy difference between the valence band edge of the SiGe layer and the vacuum level.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: January 15, 2002
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Shinichi Takagi
  • Patent number: 5363494
    Abstract: A first bus wiring line to which a plurality of first circuits each having the same bit range are connected, a second bus wiring line to which a plurality of second circuits each having a bit range smaller than that of each of the first circuits are connected, and a bus interface circuit having a buffer circuit connected between a portion of the first bus wiring line and the second bus wiring line and a dummy buffer circuit connected to the remaining portion of the first bus wiring line are arranged in an integrated circuit. Fox this reason, when a plurality of circuits having different bit ranges are connected to the bus wiring lines, the loads of the bus wiring lines can be made uniform, and a data transfer operation through the bus lines can be performed at a high speed. The operating frequency of a clock can be increased, and the performance of the system can be improved.
    Type: Grant
    Filed: October 22, 1992
    Date of Patent: November 8, 1994
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Tsuneaki Kudou
  • Patent number: 5144687
    Abstract: An image processing apparatus for medical diagnostic purposes includes a spatial shift variant filtering unit. Whole pixels of one image are filtered by different variant filtering coefficients , with each pixel being filtered by a different matrix of shift variant filtering coefficients in accordance with the location and characteristics of the original image.
    Type: Grant
    Filed: July 30, 1991
    Date of Patent: September 1, 1992
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Michitaka Honda
  • Patent number: 4962647
    Abstract: A refrigerating circuit apparatus includes a two stage compressor having an upper stage compressing cylinder and a lower stage compressing cylinder, a heat storage tank, an upper stage side variable opening expansion valve and a lower stage side variable opening expansion valve. The upper stage side variable opening expansion valve is controlled toward its closed position for executing a heat storing operation wherein heat is discharged from refrigerant to the heat storage tank. The upper stage side variable opening expansion valve is opened and the lower stage side variable opening expansion valve is closed for carrying out a defrosting operation. Heat stored in the heat storage tank is used in the defrosting operation for removing frost accumulated on an external heat-exchanger during the heating operation.
    Type: Grant
    Filed: March 3, 1989
    Date of Patent: October 16, 1990
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Eiji Kuwahara
  • Patent number: 4748596
    Abstract: In a dynamic semiconductor memory, bit line pairs and word lines are perpendicular to each other and arranged in a matrix constituted by memory cells. Dummy cells are arranged at intersections between the bit line pairs and a pair of dummy cell word lines. The capacitance of each dummy cell is half that of the memory cell. A pre-sense amplifier and a main sense amplifier are arranged in each pair of bit lines. When data is read out from a selected memory cell, the pre-sense amplifiers are simultaneously activated to perform the pre-sensing operation. However, in the main sensing operation, only one specific main sense amplifier arranged in a certain bit line pair including the bit line connected to the selected memory cell is activated.
    Type: Grant
    Filed: October 28, 1985
    Date of Patent: May 31, 1988
    Assignee: Kabushika Kaisha Toshiba
    Inventors: Mitsugi Ogura, Yasuo Itoh
  • Patent number: 4660393
    Abstract: A washing machine capable of being provided with a water filter device which includes a water inlet port, water outlet port and overflow port. The washing machine includes an operation control console provided with a water intake port and auxiliary intake port at its rear wall in correspondence to the water outlet port and the overflow port of the water filter device respectively, which supports the water filter device. The operation control console is further provided with a water intake opening and access opening at its rear portion, the water intake opening and access opening being respectively covered with a closing member and auxiliary plate when the water filter device is not attached to the control console.
    Type: Grant
    Filed: September 12, 1985
    Date of Patent: April 28, 1987
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Masanobu Yanagihara
  • Patent number: 4622142
    Abstract: A device filters impurities such as iron oxides contained in a water supply. The device includes a container having an open top end, a filter assembly housed in the container and a lid member closed over the open top end of the container. The container is partitioned into an intake chamber, a discharge chamber and an overflow passage. The lid member includes an adjusting member in contact with the filter assembly to adjust and maintain the filter assembly at a correct position within the container. The filter assembly also includes a handle member to enable a user to remove and reinsert the filter assembly from and into the container, respectively.
    Type: Grant
    Filed: July 26, 1985
    Date of Patent: November 11, 1986
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Masahiro Teranishi
  • Patent number: D337100
    Type: Grant
    Filed: April 15, 1992
    Date of Patent: July 6, 1993
    Assignee: Kabushika Kaisha Toshiba
    Inventor: Masaaki Iino