Patents Assigned to KATOH ELECTRIC CO, LTD.
  • Patent number: 10784186
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semic
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 22, 2020
    Assignee: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Patent number: 10777489
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 15, 2020
    Assignee: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Patent number: 10707156
    Abstract: An electronic device comprises a semiconductor chip, an accommodating part that accommodates the semiconductor chip, a plurality of terminals that are provided along a first side of a first surface and along a second side opposite to the first side with respect to the semiconductor chip, the plurality of terminals being electrically connected to the semiconductor chip and being exposed on the rectangular first surface of the accommodating part, and a plurality of conductive members that penetrate from the first surface of the accommodating part to the second surface opposite to the first surface.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 7, 2020
    Assignees: KATOH ELECTRIC CO., LTD., TOREX SEMICONDUCTOR LTD.
    Inventors: Shinya Sato, Yuki Yasuda, Yojiro Shiina
  • Publication number: 20190371709
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semic
    Type: Application
    Filed: October 16, 2018
    Publication date: December 5, 2019
    Applicant: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi URUSHIHATA, Takashi SHIGENO, Eiki ITO, Wataru KIMURA, Hirotaka ENDO, Toshio KOIKE, Toshiki KOUNO
  • Publication number: 20190371712
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.
    Type: Application
    Filed: October 16, 2018
    Publication date: December 5, 2019
    Applicant: Katoh Electric Co., Ltd.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Patent number: 10242937
    Abstract: To increase a current that can be supplied to an electronic element mounted on an upper surface of a semiconductor package. An electronic device includes a semiconductor chip, a package that accommodates the semiconductor chip, a plurality of terminals that is electrically bonded with the semiconductor chip and is exposed on a first surface of the package, and at least one copper post that penetrates from the first surface of the package to a second surface opposite to the first surface, and that has a cross sectional area in the direction of the first surface, which is larger than the area of the plurality of terminals on the first surface.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 26, 2019
    Assignees: KATOH ELECTRIC CO, LTD., TOREX SEMICONDUCTOR LTD.
    Inventors: Shinya Sato, Yuki Yasuda, Yojiro Shiina