Abstract: Disclosed herein is an inhomogeneity tunable erbium-doped optical fiber amplifier with a long wavelength band and method of blocking a backward amplified spontaneous light emission in the same. The optical fiber amplifier includes a control device situated between a first amplification stage and a second amplification stage for controlling an isolation rate of a backward amplified spontaneous light emission being propagated from a second amplification stage to the first amplification stage. The method blocks a backward amplified spontaneous light emission in a two-stage inhomogeneity tunable erbium-doped optical fiber amplifier with a long wavelength gain band, in which the backward amplified spontaneous light emission being propagated from a second amplification stage to a first amplification stage is blocked, and an isolation rate of the backward amplified spontaneous light emission is controlled according to the intensity of an optical signal inputted to the first amplification stage.

Abstract: Provided is an organic electroluminescent (EL) device including a substrate, a transparent electrode formed on the substrate, an organic light-emitting layer formed on the transparent electrode, a metal electrode formed on the organic light-emitting layer, a first insulating layer formed on the metal electrode, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, an organic semiconducting layer formed on the second insulating layer, a source electrode connected to one end of the organic semiconducting layer on the second insulating layer and connected to the metal electrode, and a drain electrode connected to the other end of the organic semiconducting layer on the second insulating layer.

Abstract: A method of manufacturing a large-sized thin film transistor liquid crystal display panel in which a plurality of unit thin film transistor liquid crystal display panels are fabricated having a predetermined size on a polyimide substrate. A predetermined number of the unit thin film transistor liquid crystal display panels are arranged in a form of a matrix. The unit thin film transistor liquid crystal display panels are bonded or tiled by using an epoxy resin on a glass substrate to achieved the large-sized thin film transistor liquid crystal display panel. The interface between the unit thin film transistor liquid crystal display panels are filled up with polyimide. Gate bus lines and drain bus lines of the unit thin film transistor liquid crystal display panels arranged in the form of the matrix are electrically connected.

Abstract: A dynamic random access memory (DRAM) with low noise characteristics comprises a plurality of memory cells each consisting of a pair of reference memory cells respectively arranged between a word line and a pair of adjacent bit lines. The reference memory cells store signals of opposite levels corresponding to one bit of information. Each of the reference memory cells consists of a capacitor and switching transistor. One end of the capacitor is connected to the collector of the transistor. The other end of the capacitor is connected to one of the pair of bit lines adjacent thereto. The base of the transistor is connected to the word line, and the emitter of the transistor is completed to receive a reference voltage.

Abstract: There are disclosed a semiconductor device having electrical elements buried a SOI substrate and a manufacturing method thereof, the manufacturing method of the invention comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon la

Abstract: A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.

Abstract: Disclosed is a low power consumption word line driver that satisfactorily operates even with the threshold voltage variations. A load FET comprises a depletion FET (J5) and enhancement FET (J6). The drain, gate and source of the depletion FET are connected in parallel to those of the enhancement FET. An enhancement FET (J7) is provided to charge a word line. The drains of the depletion FET and enhancement FET J5 and J6 are connected to ground voltage, the gates to the series connecting point of the preceding circuit part, and the sources to the drain of the drive FET J7 for output. The source of the drive FET J7 is connected to voltage source.

Abstract: There is disclosed a method for manufacturing a semiconductor substrate having a compound semiconductor layer on a single-crystal silicon wafer, the method comprising the steps: sequentially forming first and second compound semiconductor epitaxial layers on a compound semiconductor wafer; forming a first silicon oxide layer on the second compound semiconductor epitaxial layer at a predetermined low temperature and depositing a poly-crystal silicon layer on the first silicon oxide layer; removing portions of the larminated layers by using a etching technique to form grooves on the compound semiconductor wafer; depositing a second silicon oxide layer overlying thereon at a predetermined low temperature; etching back horizontal portions of the second silicon oxide layer to form side walls in each of the grooves and polishing the polysilicon layer to form a planar surface thereon; bonding the planar surface and the single-crystal silicon wafer by using a thermal process technique; removing the compound semicondu

Abstract: A memory cell for use in a SRAM improving the operating characteristics and capable of high density is described. In the its construction, the data is stored to a cell latch which includes load resistances and driving FETs, and a transmission FET is turned "ON" in case that a word line is selected and simultaneously electrically connects a bit line with the cell latch. A reading FET transmits the memorized contents of the cell latch to the transmission FET during reading operation of the memory cell and a writing FET stores the data of the bit line into the cell latch during writing operation of the memory cell. Thus, the predominant operating characteristics with respect to the threshold voltage variations among device parameters of FET can be obtained, and the breakdown phenomenon of the stored data can be prevented by separating the cell latch and the bit line in the memory cell.

Abstract: A multiplexer having an enable/disable control circuit which gates the enable/disable control signal with channel select control signals, and the resulting signal is applied to the data input gates, thereby reducing the number of inputs to the data input gates. This simplifies the circuitry and reduces the current requirements, thereby improving response time and reducing signal distortion.

Abstract: A method for reducing the line widths produced by patterning a semiconduc substrate with a multilayer resist mask employs a `spacer`-forming oxide layer which is non-selectively formed over the mask structure after an aperture for exposing a lower resist layer has been formed in an upper portion of the multilayer mask, but prior to etching a lower resist layer. The oxide layer is subjected to a dry systemic etch to vertically remove material of the oxide layer down to the surface of the lower resist layer. Because of the substantial step coverage of the oxide layer, a `spacer` or `stringer` portion remains along the sidewalls of the original aperture in the upper portion of the mask, whereby the dimensions of the exposure window are reduced. Retaining this sidewall spacer as an integral part of mask structure permits narrower line widths to be replicated in the underlying substrate.

Abstract: A process for formation of a GaAs MESFET for use in digital IC and MMIC is disclosed, the MESFET having a high operating speed and low noise characteristics. A multilayer resist comprising a nitride film, a photo resist, a titanium deposition layer, and a SiO layer made by SOG (spin-on-glass) is formed, and a gate which is formed in the length of 0.7-1 .mu.m by applying the photo transfer method is transcribed in the length of 0.3-0.5 .mu.m. The pattern of the gate is transcribed by etching it down to GaAs, and the place for the positioning of the T-shaped gate is defined by depositing tungsten silicide and by side-etching the photo resist. The T-shaped gate is manufactured by electroplating gold, and by lifting off the rest of the portions. The source and drain are then formed in a self-aligned manner by ion-implanting to a high concentration, and then a heat treatment is carried out to make active.

Abstract: A transport device for handling wafers of different diameters utilized in the manufacture of semiconductors. A robotic arm is equipped with a fork-shaped wafer support board and an arm slide movable relative to the robotic arm. The fork-shaped end of the support board is provided with fixed pins on one side to support wafers and on another side with plate springs carrying pins which can be depressed by the weight of a wafer to accommodate larger size wafers. The device permits wafers of different diameters accurately and safely to be transferred from its center to a predetermined station without the need for changing the wafer support board or correction of the robotic arm.