Abstract: Some aspects of the present disclosure relate to an apparatus, a PLL and an electronic device. The apparatus comprises a voltage-to-current (V2I) converter, a current controlled oscillator and a compensation current. The V2I converter is operable to receive a first voltage and generate a first current based on the first voltage. The current controlled oscillator is coupled to the V2I converter and operable to generate an oscillation signal based on a second current from or to the V2I converter. The compensation circuit is coupled to the V2I converter and operable to receive a third current from or to the V2I converter. The second and third currents vary in response to at least one of temperature variation and supply voltage variation of the apparatus. Variation direction of the third current is opposite to variation direction of the second current and different frequencies may be provided for a low supply voltage domain.

Abstract: Methods and circuitry for relatively low-speed bus time stamping and triggering for use in acoustic object and gesture detection and recognition are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that includes a data line and a clock line. The master device generates and controls a clock signal on the clock line and sends a synchronization command over the data line to the slave devices. The master device receives timestamp and/or other information corresponding to events detected at each slave device, such as a detected acoustic wave reflected from an object. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can use the event times to derive positions and gestures associated with detected objects.

Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.

Abstract: Example embodiments of the present disclosure relate to a line driver apparatus. In some example embodiments, an apparatus is provided. The apparatus includes a capacitive feed-through module and a driving module. The capacitive feed-through module includes a first pre-driver operable to receive input differential signals and delayed signals of the input differential signals, generate first drive signals from the input differential signals and the delayed signals, and equalize the first drive signals. The capacitive feed-through module also includes a capacitance reducing module arranged between the first pre-driver and transmission lines and operable to reduce parasitic capacitance at the transmission lines in response to the first drive signals. The driving module is coupled to the transmission lines and operable to generate output differential signals from the input differential signals for transmission on the transmission lines.

Abstract: A bridge chip receives a first data stream compliant with the first multimedia communication standard. The first data stream includes first video data of a first incoming video frame, second video data of a second incoming video frame, and information describing a transfer function for the second video data, the information included in a video blanking interval of the first incoming video frame. The bridge chip extracts information describing a transfer function for the second video data. The bridge chip then generates a second data stream compliant with the second multimedia communication standard. The second data stream includes the first video data in a first outbound video frame, the second video data in a second outbound video frame, and the extracted information describing the transfer function for the second video data. Finally, the generated second data stream is transmitted to a destination device.

Abstract: A sink device transmits capabilities information associated with the sink device to the source device. The source device, responsive to receiving the capabilities information of the sink device generates a multimedia stream, and transmits the generated multimedia stream to the sink device to be output to the user. The sink device identifies a portion of the capabilities information that has changed and transmits to the source device a notification notifying the source device that a portion of the capabilities information has changed. The source device transmits a request for the portion of the capabilities information that has changed to the sink device. The sink device responsive to receiving the request transmits the portion of the capabilities information that has changed to the source device. The source device then modifies the multimedia stream output to the sink device based on the portion of the capabilities information that has changed.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

Abstract: A direct digital synthesizer (DDS) is controlled by a suitably configured programmable logic device (PLD). The DDS includes a digital analog converter (DAC), and a coupled driver/buffer configured to drive relatively high capacitive loads with substantially rail to rail sinusoidal driver output signals and with little to no waveform distortion. The DAC includes a PMOS and NMOS DACs, and a switch configured to select the PMOS DAC for negative portions and the NMOS DAC for positive portions of an output analog signal generated by the DAC. The driver includes a pair of input differential amplifiers, PMOS and NMOS structures, which may be variable, and a pair of variable current sources. The PLD controls variable elements of the DDS to adjust the achievable positive and negative slew rates of the DDS, independently of one another, to reduce or eliminate risk of signal distortion while maintaining substantially stable rail to rail output.

Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.

Abstract: A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.

Abstract: Embodiments relate to inserting a preamble code as a preamble of a sub-frame of encrypted data to indicate rekeying is to be performed at a source device and to indicate data of the sub-frame and subsequent sub-frames is encrypted. A sink device authenticates a source device using an authentication and encryption protocol. The sink device receives a data stream including audio data. At least a portion of the received audio data is encrypted and the encrypted audio data is packetized into sub-frames. The sink device inserts a first preamble code as a preamble of a sub-frame to indicate rekeying is to be performed at the source device according to the authentication and encryption protocol, and to indicate that the audio data in a payload of the sub-frame and payloads of subsequent sub-frames is encrypted. The sink device transmits the packet to the source device via a first data link.

Abstract: Systems and methods for polarization converters are disclosed. An example wireless communication system includes a first transceiver module of a wireless communication system configured to form one or more linearly polarized communication links with a second transceiver module of the wireless communication system, and a polarization converter positioned between the first and second transceiver modules and configured to convert the one or more linearly polarized communication links to circularly polarized communication links. The polarization converter includes first and second frequency selective surfaces (FSSs) formed from respective first and second metalized layers of a printed circuit board (PCB), each FSS includes an array of capacitive patches and inductive traces forming an array of unit cells, and each unit cell of the second FSS is aligned with each unit cell of the first FSS.

Abstract: Systems and methods for dual channel polarization filter structures are disclosed. An example wireless communication system includes a first transceiver module of a wireless communication system configured to form one or more linearly polarized communication links with a second transceiver module of the wireless communication system, and a dual channel polarization filter structure positioned between the first and second transceiver modules and configured to filter the one or more linearly polarized communication links to produce corresponding one or more filtered linearly polarized communication links. The dual channel polarization filter structure includes first and second filter channels each formed from three structural layers including at least one metalized layer printed circuit board (PCB) disposed between the remaining two structural layers, and each filter channel includes an array of filter elements each comprising at least one metamaterial absorber arrangement.

Abstract: Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.

Abstract: Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency.

Abstract: Various techniques are provided to efficiently implement deterministic read back and error detection for programmable logic devices (PLDs). In one example, a PLD includes an array of memory cells arranged in rows and columns, where at least one row includes an enable bit. The PLD further includes an address logic circuit configured to selectively assert the columns of the array by respective address lines. The PLD further includes a register configured to store a value of the enable bit in response to an assertion of an address line corresponding to the enable bit. The PLD further includes a read back circuit configured to selectively provide, for each memory cell, a data bit value stored by the memory cell or a predetermined data bit value based at least on the stored value of the register. Additional systems and related methods are provided.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.

Abstract: Various techniques are provided to implement hysteresis control for programmable logic devices (PLDs). In one example, a PLD includes a hysteresis control circuit configured to generate a hysteresis control signal based on a core voltage and an input/output (I/O) voltage. The PLD further includes an I/O cell associated with an I/O fabric of the PLD and powered by the I/O voltage. The I/O cell includes a first buffer circuit configured to receive an input voltage and generate a first buffer voltage based on the input voltage. The I/O cell further includes a hysteresis generator configured to generate a hysteresis voltage based on the hysteresis control signal and the I/O voltage. The I/O cell further includes a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the hysteresis voltage. Related methods and systems are provided.

Abstract: Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

Abstract: In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies (e.g., DC-to-DC converters), ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. In addition, the controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.