Patents Assigned to Lattice Semiconductor Corporation
  • Patent number: 9819174
    Abstract: Techniques are provided to control hotswap operations with programmable logic devices (PLDs). In particular, a MOSFET is provided to limit an in-rush current drawn from a power supply by capacitive components of an electronic assembly when it is plugged into the live, power supply. A controller with an algorithm is provided to control the MOSFET based on the in-rush current detected at the MOSFET. As such, a feedback control loop is established to selectively bias the gate of the MOSFET based on the detected in-rush current. The algorithm may limit the in-rush current based on a Safe Operating Area (SOA) of the MOSFET. The hotswap process may include multiple phases each with a voltage and/or current limit modeling the voltages and currents of the SOA. The algorithm may transition through the phases with the respective current and/or voltage limits during the hotswap process.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: November 14, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Christopher W. Dix, Cleo Mui, Cheng-Jen Gwo, Joel Coplen, Srirama Chandra
  • Patent number: 9820389
    Abstract: In one embodiment, a ball grid array (BGA) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors. The outer rectangular ring has empty locations having no connectors. Some of those empty locations define depopulated sets that divide the outer rectangular ring into a number of different contiguous sets of locations having connectors that enable pin escape for connectors of the device's BGA.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: November 14, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventor: Ban Pak Wong
  • Patent number: 9811495
    Abstract: An apparatus for interfacing with a multimedia communication link comprises a half-duplex translation layer circuit operating in half-duplex and a full-duplex link layer circuit to communicate over a control bus of the multimedia communication link in full duplex. The apparatus further comprises an arbitration circuit communicatively coupled between the half-duplex translation layer circuit and the full-duplex link layer circuit, the arbitration circuit to control data flow between the half-duplex translation layer circuit and the full-duplex link layer circuit. The arbitration circuit provides interface and signaling rules for transmitting packets from the half-duplex translation layer circuit to the full-duplex link layer circuit, receiving packets via the full-duplex link layer circuit at the half-duplex translation layer circuit, and resolving conflict arising due to bidirectional data flow at the arbitration logic.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 7, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jiong Huang, Lei Ming, Gyudong Kim, Young Il Kim
  • Publication number: 20170317829
    Abstract: Embodiments relate to inserting a preamble code as a preamble of a sub-frame of encrypted data to indicate rekeying is to be performed at a source device and to indicate data of the sub-frame and subsequent sub-frames is encrypted. A sink device authenticates a source device using an authentication and encryption protocol. The sink device receives a data stream including audio data. At least a portion of the received audio data is encrypted and the encrypted audio data is packetized into sub-frames. The sink device inserts a first preamble code as a preamble of a sub-frame to indicate rekeying is to be performed at the source device according to the authentication and encryption protocol, and to indicate that the audio data in a payload of the sub-frame and payloads of subsequent sub-frames is encrypted. The sink device transmits the packet to the source device via a first data link.
    Type: Application
    Filed: December 7, 2015
    Publication date: November 2, 2017
    Applicant: Lattice Semiconductor Corporation
    Inventors: Ju Hwan Yi, Hoon Choi
  • Patent number: 9800642
    Abstract: A transmitter and receiver for communication of multimedia streams across a multi-lane communications link. The transmitter packetizes multimedia streams according to a link layer protocol and distributes the packets across multiple lanes of a communications link. The entire packet, including the header and payload, can be distributed across the lanes in an ordered sequence to increase utilization of the communication lanes. The transmitter may also packetize multiple multimedia streams and intermix the packets across the lanes of the communication lane. The receiver extracts the packets that are distributed across the multiple lanes and decodes the packets into the multimedia streams.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 24, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Ju Hwan Yi, Hoon Choi
  • Patent number: 9800886
    Abstract: A transmitting device for communicating via a multimedia communication link includes a compression circuitry that receives blanking period data corresponding to blanking states of video blanking periods. The compression circuitry compresses the blanking period data into compressed blanking period data. The transmitting device also includes an interface that transmits signals corresponding to the compressed blanking period data via one or more multimedia channels of the multimedia communication link.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: October 24, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Hoon Choi, Ju Hwan Yi
  • Patent number: 9772856
    Abstract: In one embodiment, a system has a master programmable device (PD) with native dual-boot capability and one or more slave PDs with no native dual-boot capability. A master golden image includes an embedded dual-boot function. During power-up, each PD copies its primary image into its volatile configuration memory and determines whether the primary image is valid. When the master's configuration engine detects an invalid master primary image, then the master's native dual-boot capability enables the master to implement a system-reboot procedure, which includes copying the master golden image from an external memory device into the master's volatile configuration memory and launching the embedded dual-boot function, which in turn copies the slave golden images from the external memory device into the slaves' volatile configuration memories before enabling other master-golden-image functions. Significant system reliability and robustness are achieved without provisioning every PD with native dual-boot capability.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 26, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Srirama Chandra, Cleo Mui, Cheng Jen Gwo, Saurabh Chheda
  • Patent number: 9769417
    Abstract: Aspects relate to transmission of metadata from a source to a sink device, and optionally through one or more intermediaries. A source device encodes metadata into what would have been a blanking area of a field to be transmitted, according to a current video format. The source device encodes a timing for an active video data signal that is modified from a timing that would be used only for transmission of video data at a current resolution. A separate indicator from the source, or a negotiation between source and sink allows the sink to determine what part of the data indicated as being active video data is metadata, and to use that metadata for controlling aspects of the video display, and to use other parts of the received video data as video data for display. A sink can signal supported capabilities to a source.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: September 19, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Sergey Yarygin, Laurence A Thompson, Chandlee B Harrell, Gyudong Kim
  • Patent number: 9743017
    Abstract: Embodiments of the invention are generally directed to an integrated mobile desktop. An embodiment of an apparatus includes a display chip to receive graphical data and produce video display signals; and a logic chip to receive data from a mobile device and the video display signals from the display chip to generate a display including at least a portion for a representation of a display of the mobile device. The logic chip provides for integration of operations for the apparatus and the mobile device using the generated display.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: August 22, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Marshall Goldberg, Wooseung Yang, Ju Hwan Yi, Seung Jong Lee
  • Patent number: 9735761
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 15, 2017
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
  • Patent number: 9728273
    Abstract: In one embodiment, a BIST (built-in self-test) engine performs BIST testing of embedded memory in an integrated circuit device (e.g., an FPGA) via an (e.g., hard-wired, dedicated, low-latency) bus from the configuration bitstream engine. During BIST testing, data is written into the embedded memory at-speed, which may require the bitstream engine to produce a higher frequency than originally used for configuration. Between consecutive write operations, the BIST engine is capable of reading the previously written set of data from the embedded memory and comparing that read-back data with the corresponding original set of data to determine whether a BIST error has occurred. By performing back-to-back write/read-back operations faster than the configuration speed and using a dedicated W/RB bus, BIST testing can be optimally performed without false-positive-invoking delays and undesirable resource utilization.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 8, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Kanad Chakraborty, Naveen Purushotham
  • Patent number: 9722612
    Abstract: Techniques are provided to permit a programmable logic device (PLD) to comply with a communication standard before the PLD is fully configured. In one example, a method includes programming a first portion of a programmable logic device (PLD) with first configuration data. After the first portion is programmed, the first portion is operated in accordance with a communication standard to exchange data with a host system while a second portion of the PLD is programmed with second configuration data.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: August 1, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Umesh Ananthiah, Tramie Tran, Jamie Freed
  • Patent number: 9722643
    Abstract: Embodiments relate to enhancing echo cancellation in a transceiver integrated circuit (IC) for full-duplex communication by providing a signal path connected to a dummy driver that replicates a signal path between a main driver and a counterpart transceiver IC to cause a duplicated signal generated by the dummy driver to more closely replicate a sending signal generated by the main driver. The signal path connected to the dummy driver includes circuit elements having transmission line parameters and RLC parameters that replicate transmission line parameters and RLC parameters of circuit elements in the signal path between the main driver and the counterpart transceiver IC.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: August 1, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jiandong Ke, Kai Lei, Yi Gao, Qi Zhou, Qiming Wu, Kai Zhou
  • Patent number: 9716491
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: July 25, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Brad Sharpe-Geisler, Senani Gunaratna, Ting Yew
  • Patent number: 9710578
    Abstract: Various techniques are provided to configure embedded hardware resources of a programmable logic device (PLD). In one example, a method includes receiving configuration information for a plurality of hardware modules of an embedded hardware block of a PLD. The configuration information is received from a user of a computer system external to the PLD. The method also includes generating a plurality of models of the hardware block. The method also includes merging the generated models into a combined model of the hardware block. The combined model includes the configuration information received for the hardware modules of the hardware block. Related systems and additional techniques are also provided.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: July 18, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Debaprosad Dutt, Jamie Freed, Harish Venkatappa, Pradeep Lenka, Minghao Ni
  • Patent number: 9703729
    Abstract: Embodiments of the present disclosure are related to identifying the orientation of a multimedia link connected between a source device and a sink device. A sink device includes a plurality of pins that are configured to interface with a plurality of pins of the multimedia link. The sink device identifies based on the values of one or more pins of the plurality of pins of the sink device whether the multimedia link is connected to the sink device. Further, the sink device determines an orientation of the multimedia link connected to the sink device. The multimedia link can be in one of two orientations, straight or flipped. The sink device may communicate the orientation of the multimedia link to the source device. The source device may perform lane mapping based on whether the multimedia link is in the straight or flipped orientation.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: July 11, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Shrikant Ranade, Gyudong Kim, Chandlee B Harrell
  • Patent number: 9699469
    Abstract: A solution for adaptively processing a digital image with reduced color resolution is described herein. A source device pre-processes a video frame with reduce color resolution by remapping luma components and chroma components of the video frame, and encodes the pre-processed video frame. The source device remaps a half of luma components on a scan line of the video frame onto a data channel of a source line to an encoder and remaps the other half of the luma components on the scan line to another data channel of the source line. The source device remaps the corresponding chroma components onto a third data channel of a source line. By using a data channel conventionally configured to transmit chroma components, the solution enables a video codec to adaptively encode a digital image with reduced color resolution without converting the digital image to full color resolution before the encoding.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: July 4, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventor: Laurence Alan Thompson
  • Patent number: 9692414
    Abstract: In one embodiment, an inverter generates an inverted clock signal using (i) first P-type and N-type transistors connected in cascode between supply and ground nodes and (ii) control circuitry receiving different phase-offset input clock signals that ensure that the cascode-connected transistors are never even partially on at the same time, thereby preventing crowbar current from occurring through the cascode-connected devices. In one implementation, the control circuitry has two P-type transistors and two N-type transistors configured to receive three phase-offset input clock signals to prevent crowbar current in the inverter. The control circuitry has pass transistors that selectively allow one of the phase-offset input signals to be applied to the gate of one of the cascode-connected transistors with minimal delay, thereby enabling the inverter to operate properly over a relatively wide range of input clock frequencies.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: June 27, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventor: Edward Miller
  • Patent number: 9692688
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining delay windows for connections in a routing of a design for a PLD, identifying invalid connections in the routing based, at least in part, on the determined delay windows, and routing the invalid connections using a dual wave maze routing process to provide a delay-specific routing for the design. The delay-specific routing may be used to generate configuration data to configure physical components of the PLD, and the configuration data may be used to program the PLD to conform to the timing constraints of the design and/or PLD.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: June 27, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventor: Qinhai Zhang
  • Patent number: 9693046
    Abstract: Embodiments of the invention are generally directed to a multi-view display system. An embodiment of an apparatus includes a display screen to display multiple views simultaneously, and a controller to control the views presented on the display screen. The apparatus is configurable by the controller to provide multiple view settings, the view settings including a first setting in which the apparatus provides a single view to each viewer of the display screen and a second setting in which the apparatus provides a first view to a first viewer of the display screen and a second view to a second viewer of the display screen. A first filtering element filters views presented to viewers of the display screen such that an intended view is displayed to one or more viewers.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: June 27, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Christopher Unkel, Lawrence L. Butcher, James G. Hanko, J. Duane Northcutt, Brian K. Schmidt, Edwin C. Seim