Abstract: An SRAM semiconductor device is disclosed in which an access transistor is an nMOS TFT to thereby reduce cell size and to improve low Vcc characteristics. The semiconductor device comprises a gate electrode of a drive transistor formed on the semiconductor substrate, with a first gate insulating film therebetween. A first impurity region is formed on the substrate on opposite sides of the gate electrode of the drive transistor. An insulating film is formed on the entire surface of the substrate and has a contact hole exposing part of the gate electrode of the drive transistor. A semiconductor layer is formed on the insulating film in connection with the gate electrode of the drive transistor through the contact hole; a second gate insulating film is formed on the semiconductor layer; and a gate electrode of an access transistor is formed on the second gate insulating film. Further, a second impurity region is formed in the semiconductor layer on opposite sides of the access transistor gate electrode.

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract: An apparatus for detecting errors in an asynchronous data receiver and transmitter include a first sample block for sampling a received serial data bit, a first storing part for storing a first value of the serial data bit sampled by the first sample block for a predetermined time, a second sample block for sampling the received serial data bit, a second storing part for storing a second value of the serial data bit sampled by the second sample block for a predetermined time, and a comparing part for receiving and comparing the first value and the second value of the serial data bit stored in the first and second storing parts and outputting an error signal if the first value and the second value are not identical.

Abstract: A method of forming a wiring in a semiconductor device having a semiconductor substrate includes the steps of forming a barrier layer on the semiconductor substrate, forming a first metal layer on the barrier layer, forming a first alloy layer containing the first metal layer and a second metal layer on the first metal layer, and forming a second alloy layer by diffusing between the first metal layer and the first alloy layer.

Abstract: A complementary clock generator and a method for generating complementary clocks are disclosed. A complementary clock generator according to the present invention includes a first inverter, a first transmitting switch and a second transmitting switch. The first inverter outputs inverted clock signals by inverting input clock signals. The first transmitting switch has an input terminal, an output terminal, a first control input terminal and a second control input terminal, and connects the input terminal to the output terminal when the input clock signal reaches the first control input terminal and the inverted clock signal from the first inverter reaches the second control input terminal.

Abstract: Method for fabricating a solid state image sensor, which can improve a charge transfer efficiency of an end terminal, including the steps of (1) providing a first conduction type substrate having a second conduction type well and a BCCD formed therein for an end terminal, (2) continuously increasing impurity concentrations in a region of the substrate in which a floating diffusion region is to be formed and in a portion of an area of other substrate in which the regions are are to be formed for improving a horizontal charge transfer efficiency, and (3) forming transfer gates, an output gate, and reset gate on the substrate, and the floating diffusion region and a reset drain region in the BCCD, respectively.

Abstract: Low power CMOS circuit provided with CMOS devices, is disclosed, for minimizing a power consumption in a standby mode, including PMOS transistors having drains connected to a power supply voltage and NMOS transistors having sources connected to a ground voltage, both of the PMOS transistors and the NMOS transistors being adapted to be applied of a back bias voltage in a standby mode, wherein the PMOS transistors and the NMOS transistors are formed to have high gamma factors.

Abstract: Nonvolatile memory capable of programming and erasure and method for fabricating the same, the method comprising the steps of (1) forming an oxide film on a first conduction type semiconductor substrate, (2) conducting an annealing in an NO or N2O ambient to convert the oxide film into a vertical lamination of a first silicon oxynitride region containing nitrogen and a second silicon oxynitride region containing relatively less nitrogen compared to the first silicon oxynitride region formed on the substrate, (3) patterning a gate electrode on the second oxynitride region, (4) forming second conduction type source, and drain impurity diffusion regions in surfaces of the substrate on both sides of the gate electrode, whereby facilitating a simple and easy fabrication process, a low programming voltage, a high performance, and a high device reliability.

Abstract: Provided with a method of forming a capacitor of semiconductor devices including the steps of: forming a first insulating layer having a plurality of contact holes on a semiconductor substrate; forming a plug in each of the contact holes; sequentially forming a second insulating layer and a mask layer on the entire surface of the semiconductor substrate; selectively removing the mask layer to form a plurality of first mask patterns having a first line width between the plugs; selectively removing the first mask pattern to form second mask patterns having a second line width smaller than the first line width; removing the second insulating layer by using the second mask patterns as a mask so as to expose the plugs; sequentially forming a conductive layer and a third insulating layer on the entire surface of the semiconductor substrate for the sake of electrical connection to each plug; removing materials overlying the second insulating layer to expose the surface of the second insulating layer, and forming a l

Abstract: A method for fabricating a semiconductor device includes the steps of forming a field oxide layer on a field region of a semiconductor substrate where a field region and an active region are defined, forming a polycide layer on the entire surface of the semiconductor substrate including the field oxide layer and selectively removing the polycide layer to form a gate electrode and a lower electrode of a capacitor, successively forming a dielectric layer and a polysilicon layer on the entire surface including the lower electrode of the capacitor and patterning the dielectric layer and the lower electrode to form an upper electrode pattern and a resistor pattern, and forming an insulating layer to cover the resistor pattern and forming another polycide layer on the upper electrode of the capacitor.

Abstract: A mobile communication system includes a demodulator demodulating an interleaved data signal and outputting a demodulated data. A deinterleaver data array receives and deinterleaves the demodulated interleaved data and outputs a deinterleaved demodulated data. A memory stores the deinterleaved demodulated data and a Viterbi decoder receives the deinterleaved demodulated data from the memory. The Viterbi decoder corrects any error in the deinterleaved demodulated data. A controller accesses unit data outputted from the demodulator to the deinterleaver data array and the memory, respectively. An address generator receives an externally applied start address signal and outputs address signals corresponding to a block size to the deinterleaver data array. An input/output unit is coupled to the demodulator, the deinterleaver data array, and the controller. The input/output unit controls data input/output operations.

Abstract: A low-voltage A/D converter is provided which improves resolution by applying a sampling block at input terminal of a comparator to 0˜Vdd period.

Abstract: A FOD (First-One-Detector) circuit for detecting the number of leading zeros counted from a most significant bit to a first one in a binary number includes a plurality of sub-FODs respectively having a plurality of unit blocks connected in cascade, when a fraction input is less than 16 bits, depending on the number of bits and respectively provided with a plurality of transmission transistors. When the fraction input is more than 16 bits, the plurality of sub-FODs respectively output the number of leading zeros with regard to predetermined bits of fraction inputs, and a determinative signal for determining whether the fraction inputs are all zeros. The sub-FODs respectively further include an encoding circuit for encoding the number of leading zeros outputted from the plurality of sub-FODs and the determinative signal and outputting the resultant number of leading zeros. The FOD circuit employs a fewer number of transistors and realizes a faster normalization by a quick detection of leading zeros.

Abstract: A method of fabricating a gate electrode having dual gate insulating film includes the steps of sequentially providing a substrate having a first portion and a second portion, forming a first insulating film on the first portion of substrate, a first conductive film on the first insulating film and a second insulating film on the first conductive film, forming a third insulating film on the second portion of the substrate, forming a second conductive film on the second and the third insulating films, and patterning the first and the second conductive film to form a gate electrode.

Abstract: A ball grid array semiconductor package includes a first substrate having a plurality of first holes and a recess, a second substrate having a plurality of second holes and a third hole, a plurality of conductive balls connecting the first and second substrates by filling the first and second holes, a semiconductor chip on the recess of the first substrate, a first conductive wiring portion electrically connecting the semiconductor chip and the conductive balls, and an encapsulating member encapsulating the semiconductor chip.

Abstract: A solid state image sensor includes a semiconductor substrate and a plurality of transfer lines over the substrate and receiving clock signals, at least one of the plurality of transfer lines having a transparent conductive material. A plurality of transfer electrodes are connected to the transfer lines and a plurality of photoelectric conversion regions under a surface of the substrate generate image signals. A plurality of charge transfer regions under the surface of the substrate transfer the image signals from the photoelectric conversion regions in response to the clock signals from the transfer lines.

Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, and including opposing edge portions and a middle portion. An insulating film is formed on the surface of the gate electrode having a greater thickness on one of the gate edge portions. An active region is formed on the surface of the insulating film and the exposed substrate. The active region includes an off-set region, a channel region, a source region, and a drain region.

Abstract: A reference voltage generating circuit generates a reference voltage by using a voltage difference of a PMOS transistor, to thereby exclude the reliability of a back-bias voltage. The reference voltage generating circuit includes a reference voltage generating unit which generates a first reference voltage with respect to a power supply voltage, and a level converting unit which converts the first reference voltage applied from the reference voltage generating unit to a second reference voltage with respect to a ground voltage.

Abstract: A non-linear digital-to-analog converter is disclosed, which realizes non-linear output with overlapped resistor string. The non-linear digital-to-analog converter includes a first reference voltage select switching portion for selectively outputting first and second reference voltages Vh1 and Vc1 from externally applied reference voltages Vref[1, . . . 2N/2] and third and fourth reference voltages Vh2 and Vc2 from externally applied reference voltages Vref[0, . . . 2N/2−1] if N bit digital value is input, a resistor string block for outputting Vh[0, . . . 2N/2−1] number of level voltages, Vc[0, . . . 2N/2−1] number of level voltages, and V1[0, . . . 2N/2−1] number of level voltages from any one of the reference voltages Vh1 and Vc1 and any one of the reference voltages Vh2 and Vc2, a second reference voltage select switching portion for outputting a first analog conversion voltage V1 from the Vh[0, . . .

Abstract: A semiconductor device having a plurality of transistors connected in series in a semiconductor substrate, the device includes first and second gate electrodes on the semiconductor substrate, a punch-through stop layer in the semiconductor substrate below the first gate electrode at a predetermined depth, and first, second, and third heavily doped impurity regions in the semiconductor substrate at both sides of the first and second gate electrodes.