Abstract: A method for designing an Application Specific Integrated Circuit (ASIC) structure on a semiconductor substrate, includes (a) defining a class of circuit designs, the class having a common design part shared within the class and a custom design part variable for individual designs in the class, (b) allocating a set of bottom layers and a set of top metal layers to implement the common design part, the allocated sets of bottom layers and top metal layers having a fixed pattern for the class, and (c) implementing the custom design part using metal layers above the allocated set of bottom layers and below the allocated set of top metal layers. The method may further includes characterizing the ASIC for the common design and using the fixed patterns of the allocated set of bottom layers and the allocated set of top metal layers.

Abstract: A signal testing implementation provides significant advantages over conventional signal testing techniques. According to an exemplary embodiment, an apparatus for enabling signal testing such as SCSI signal testing in a test configuration includes a portable cable environment having a plurality of cables exhibiting a plurality of lengths and impedances. A user can selectively connect any one of the cables between a host device such as a server and a target device such as a disk subsystem. Signal measurement connectors which are connectable to the portable cable environment may be provided. According to an embodiment, each of the signal measurement connectors includes one or more test measurement points to enable collection of signal testing results.

Abstract: A method of chemically altering a silicon surface and associated dielectric materials are disclosed.

Abstract: Methods for calculating delays for cells in ASICs are disclosed. In the present invention, delays are computed by considering not only the process (P), voltage (V), temperature (T) but also input ramptime (R) and output load or fanout (F) of the cells by fitting the delay at four corner points for derated PVT condition into a non-linear equation which is a function of P, V, T, R and F. Thus, the delay is a five dimensional characterization, and the characterization is split into (P,V,T) characterization and (R,T) characterization to reduce the characterization time and resources. The present invention provides for accurate calculation of delays for cells in ASICs.

Abstract: The present invention is directed to a uniform airflow diffuser for utilization in a process chamber, such as a process chamber utilized in the manufacture of semiconductor chips. The uniform airflow diffuser is suitable for generating a back flow of air sufficient to cause the airflow to be distributed across the airflow diffuser. The resultant build-up in pressure in the plenum area may result in uniform airflow through a plurality of holes included in the airflow diffuser yielding substantially laminar airflow through the chamber.

Abstract: An apparatus comprising one or more drive portions and a controller. The one or more drive portions may each comprise one or more drives. The controller may be configured to map correctly correlating addresses to the one or more drives.

Abstract: In a computerized data storage system, when data is to be updated in a primary, or “base,” logical volume, a snapshot volume is formed from the base volume. The updates are then made to the snapshot volume, preferably while the base volume is still used to satisfy normal I/O (input/output) access requests. After the updating is complete, the snapshot volume is rolled back into the base volume. During the rollback, any remaining original data in the base volume and the updated data in either the base volume or snapshot volume are available for satisfying the normal I/O access requests. Thus, the updating appears to be instantaneous, since the entire updated data is immediately available upon starting the rollback.

Abstract: A method for leveling an exposure field of view at a peripheral edge of a substrate. The field of view is aligned to a first position at the peripheral edge of the substrate, where the field of view has an inner edge and an outer edge, relative to the peripheral edge of the substrate. Whole device patterns within the field of view are identified, and the alignment of the field of view is altered to a second position so as to place the outer edge of the field of view adjacent the whole device patterns within the field of view. Level measurement information from the field of view at the second position is acquired and stored. The field of view is realigned to the first position, and the substrate is leveled within the field of view at the first position using the level measurement information acquired from the field of view at the second position.

Abstract: A storage subsystem architecture in which front-end (host interface) control is separated from back-end (disk array) control. A plurality of front-end controller devices (FECs) and a plurality of back-end controller devices (BECs) are provided and are interconnected using storage area networking (SAN) switching devices. Each FEC and BEC includes a SAN interface. In a first preferred embodiment, the SAN interface is an InfiniBand compliant communication medium with associated switching and bus components. Alternative embodiments include a SAN interface that is pair of PCI bus interfaces each connected to one of two PCI bus backplanes. In this configuration, the SAN switch is simply the passive PCI backplane. In a second alternative preferred embodiment, redundant pairs of active SAN switch components are provided and each FEC and BEC includes a SAN interface appropriate to the particular SAN switch component selected.

Abstract: A multi-level redistribution layer trace reduces current crowding in solder bumps of an integrated circuit package. A multi-level redistribution layer trace for an integrated circuit die includes a redistribution layer trace formed on the integrated circuit die in each of a plurality of electrically conductive layers and an I/O pad formed at a termination of the redistribution layer trace so that the I/O pad extends through each of the plurality of electrically conductive layers to form an electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers. The redistribution layer trace may also be slotted to divide current flow horizontally at the electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers.

Abstract: A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.

Abstract: An apparatus for detecting a predetermined pattern of bits in a data bitstream includes a series of detecting elements (2-6), each detecting element in the series corresponding to a predetermined bit in the predetermined pattern. Each detecting element receives a data bit from the data bitstream (8), the corresponding predetermined bit in the predetermined pattern and an error signal from a previous detecting element in the series. The output of each detecting element is an error signal indicative of the number of mismatches between the data bit and the corresponding predetermined bit in the predetermined pattern, both in previous detecting elements in the series in previous clock cycles and in the current detecting element in the current clock cycle. The error signal of the final detecting element (6) of the series is coupled to a logic control element (18) for detecting that a maximum allowed level of mismatches has been detected.

Abstract: A Gaussian noise is simulated by discrete analogue ri,j. A first parameter &agr; and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on &agr;, i and j. The discrete analogue ri,j is based on a respective si,j.

Abstract: A method of displaying a net in a CAD layout for an integrated circuit chip includes steps for receiving a netlist of an integrated circuit design, displaying a CAD layout of the netlist, selecting a net segment in the CAD layout, and displaying a physical characteristics list of information items representative of physical characteristics of the net segment.

Abstract: Creation and detection of synchronization marks for a multilevel data storage medium is disclosed. A sequence of symbols is generated and the sequence of symbols is written to the multilevel data storage medium. A corresponding sequence may be generated by a detector and correlated with read data to detect the synchronization mark.

Abstract: A packaged circuit with VDDcore contacts in first positions and VSScore contacts in second positions. A redistribution layer is adjacent the integrated circuit, and overlies VDDcore and VSScore mesh layers. First contacts in the redistribution layer are positioned in alignment with the first positions, to make connections between the redistribution layer and the VDDcore contacts. Second contacts are positioned in alignment with the second positions, to make connections between the redistribution layer and the VSScore contacts. First vias are positioned in alignment with the first positions, to make connections between the first contacts and the VDD mesh layer. The traces of the VDD mesh layer are positioned in alignment with the first positions. Second vias are positioned in alignment with the second positions to make connections between the second contacts and the VSS mesh layer. The traces of the VSS mesh layer are positioned in alignment with the second positions.

Abstract: The present invention provides systems and methods for logging information regarding write operations directed to the disk being upgraded while the single disk is inoperable during the upgrade process. When the upgrade of the disk is complete, the logged information is used to update the information stored on the upgraded disk. The logged information is sufficient to update the disk contents without requiring a time consuming total reconstruction of the entire content of the disk. In one exemplary preferred embodiment, the logged information identifies a logical block numbers of the disk that are impacted by write operations processed while the disk firmware was being upgraded. Only the data corresponding to the logged logical block numbers needs be reconstructed from the redundant data on other disks of the array. This method of data reconstruction is a less time consuming process than a total reconstruction of all data on the upgraded disk.

Abstract: Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.

Abstract: The present invention is directed to a system and method for tuning retry performance of read requests of data from electronic data storage devices. In an aspect of the present invention, a method for performing a delayed read in an electronic data storage system having an initiator and a target device may include initiating a delayed read by the initiator to the target device and issuing at least one delayed read. The initiator then delays for a programmed interval before reissuing the at least one delayed read.

Abstract: A method for providing sequential initialization of redundancy data in a volume comprising the steps of: (A) defining a boundary; (B) determining a location of the data with respect to the boundary; and (C) initializing a redundancy location of the volume and writing the data and a redundancy of the data to the volume.