Abstract: A power integrity analysis integration tool for analyzing the power integrity of a semiconductor layout previously designed using a separate design tool. The power integrity analysis integration tool includes a graphic user interface that is configured to extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout. A method of designing a semiconductor layout and performing a transistor-level analysis of the power integrity of the semiconductor layout includes, first, using a design tool to design the semiconductor layout, and then using the power integrity analysis integration tool to extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout.

Abstract: Optical emission spectra from a test wafer during a plasma process are measured using a spectrometer. The plasma charging voltage retained by (detected by) the test wafer is measured after the process step is completed. The emission spectra are correlated with the plasma charging voltage to identify the species contributing to the plasma charging voltage. The optical emission spectra are monitored in real time to optimize the plasma process to prevent plasma charging damage. The optical emission spectra are also monitored to control the plasma process drift.

Abstract: A method for designing and mapping a power-bus grid in an integrated circuit. A floor plan is created by mapping wire segments of the power-bus grid to various metal layers of the IC core. Power zones which specify the current consumption of analog, digital, and memory block regions are also mapped to the IC core. A netlist of the floor plan design is generated and simulated, with the simulation returning current density and a voltage drop values in the wire segments with respect to the power zones. Calculated current density and voltage drop values are analyzed using a color map to indicate the current density and voltage drop levels of the wire segments. Power-bus wire segments are displayed in colors matched to the current density and voltage drop levels in the color map, helping the designer identify potential electromigration and voltage drop problems. The floor plan design can be modified if the calculated density and voltage drop values indicate potential electromigration or voltage drop problems.

Abstract: A drum washer has a base, a barrel support structure, and a water delivery system. A hollow drum is turned over and placed on the drum washer by inserting a spray head of the water delivery system through a hole in a top cover of the drum and into the interior of the drum. The barrel support structure holds the drum at a fixed angle while water is sprayed from the spray head onto interior surfaces of the drum. The water rinses the interior surfaces of the drum and drains out the hole in the top cover of the drum.

Abstract: A method of forming a reticle is provided. In general, a metal containing material is vaporized through simple vaporization. The metal containing material is condensed on a substrate to form a metal containing layer on the substrate. A patterned photoresist layer is formed over the metal containing layer, defining exposed metal containing layer regions and covered metal containing layer regions. The metal containing layer in the exposed metal containing layer regions is removed from the substrate, while the metal containing layer in the covered metal containing layer regions remains on the substrate to form a metal containing mask. The substrate is plasma etched. The remaining metal containing layer is removed from the substrate.

Abstract: Methods and associated structure for updating and propagating firmware updates in a multiple redundant controller storage subsystem. The methods of the present invention assure that the storage subsystem remains operable processing host system I/O requests while the redundant controllers manage the firmware update process. At least one controller of a plurality of redundant controllers in the system remains available for processing of host I/O requests as the controllers manage the firmware update process. A management client process operable on an administrative system coupled to the first of the redundant storage controllers transfers a structured firmware file to the first redundant controller. The management client need perform no further management of the update process. Rather, the controller themselves manage the process in accordance with metadata stored within the firmware file along with the programmed instructions to be updated.

Abstract: Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.

Abstract: A process for removal of a photoresist mask used to etch openings in low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and for removing etch residues remaining from either the etching of the openings or removal of the resist mask, while inhibiting damage to the low k dielectric material comprises. The structure is exposed to a reducing plasma to remove a portion of the photoresist mask, and to remove a portion of the residues remaining from formation of the openings in the layer of low k dielectric material. The structure is then exposed to an oxidizing plasma to remove any remaining etch residues from the openings in the layer of low k dielectric material or removal of the resist mask.

Abstract: In a storage environment or storage area network having multiple host devices and at least one storage array, the host devices access logical data volumes stored on the storage array through array controllers disposed in the storage array. Multiple host devices can request access to shared ones of the logical data volumes through multiple paths to multiple array controllers, but each logical data volume is controlled or owned by only one array controller at a time. Thus, ownership of shared logical data volumes is transferred between the array controllers as necessary on behalf of the requesting host devices. To prevent ownership transfers from occurring too often, however, ownership of the logical data volumes is made exclusive, or “sticky,” for a period of time after each transfer. During the exclusive ownership period of time, the ownership cannot be transferred.

Abstract: A method and apparatus are disclosed for asynchronous testing of multiport memories. In one embodiment, the apparatus includes a built-in self-test (BIST) unit coupled to a multiport memory module and configured to apply a pattern of read and write test operations concurrently to multiple ports of the memory. The pattern of test operations may be any standard or customized pattern designed to establish the functionality of the multiport memory. The test operations to different ports are clocked by different clock signals so that the clock signals may be offset relative to each other by an adjustable or preset clock skew. Certain clock skews cause transitions to occur on signal lines in the memory array at the most sensitive portion(s) of a read cycle. The timing of these transitions, in combination with the presence of high-resistivity bridge faults, sufficiently disturbs the read cycle so as to cause a read error, thereby enabling detection of the bridge faults.

Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.

Abstract: An input/output array of an integrated circuit comprises concentric rings of input/output tiles. The peripheral input/output tiles are adjacently arranged along the periphery of the integrated circuit to form a peripheral ring. Each of the peripheral input/output tiles is associated with a corresponding peripheral input/output device group having x1 number of input/output devices. Each peripheral input/output tile includes x1 number of signal contacts for coupling signals to corresponding ones of the x1 number of input/output devices, y1 number of input/output driver voltage contacts for coupling a source voltage to drivers of the x1 number of input/output devices, and z1 number of ground contacts. The interior input/output tiles are adjacently arranged within the interior of the integrated circuit to form n number of substantially concentric interior rings, where n is greater than or equal to one.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate a sorted list of permanent unique identifiers according to predetermined criteria and (ii) associate a logical identification with a physical address identifier using the sorted list. The second circuit may be configured to manage communications between a host and a target. The second circuit may (i) communicate with the host using the logical identification and (ii) communicate with the target using the physical address identifier. The communications between the host and the target may be unaffected by changes in the physical address identifier. The function of the first circuit and/or the second circuit may be implemented, among other examples, in software and/or firmware.

Abstract: A data storage system and a method of managing data in the storage system. A method of performing a write to a data storage system, including a first storage device and a second storage device, may include writing a first set of header information to a first storage device and a second storage device. The first set of header information includes a first sequence number and a second sequence number, in which the first set of header information includes a first sequence number incremented to indicate a change from the second sequence number. The method may also include returning status of completion of writing the second set of header information. Invalid data or an interruption may also be detected by examining the first and second sequence numbers. Data is written to the first storage device and the second storage device. Then, a second set of header information is written to a first storage device and a second storage device.

Abstract: A system and method for dynamically generating the topology of a storage array network by linking information concerning hosts and clusters along with information about host port adapters. Namely, each host identifies itself to all controllers and provides information in a command that allows the controller to know which host and cluster, if applicable, is associated with the host port adapter through which the command was issued. In addition, the topology is automatically updated anytime there is a change on the network such as a new device was added or a host port adapter was replaced.

Abstract: A circuit comprising a cache memory, a memory management unit and a logic circuit. The cache memory may be configured as a plurality of associative sets. The memory management unit may be configured to determine a data tag from an address of a data item. The logic circuit may be configured to (i) determine a selected set from the plurality of associative sets that produces a cache-hit for the data tag, (ii) buffer the address and the data item during a cycle, and (iii) present the data item to the cache memory for storing in the selected set during a subsequent cycle.

Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells. A different logic cone is derived for each of the multiple failing output signals at output pads.

Abstract: A first circuit and a second circuit. The first circuit may be configured to generate a first intermediate signal, a second intermediate signal, and a third intermediate signal in response to a first control signal, a second control signal, a third control signal, a reference signal and an output clock signal. The second circuit may be configured to generate an output signal in response to the first intermediate signal, the second intermediate signal, and the third intermediate signal. The output signal may indicate a lock condition between a feedback signal and the reference signal.

Abstract: Structure and associated methods of operation for an enhanced boundary scan register structure in an integrated circuit that permits flexible application of stuck-at faults or normal operation on each I/O pad of the IC. Each pad may be individually controlled to force a desired stuck-at fault or may be permitted to operate normally. The additional structure integrates with existing boundary scan register structures to minimize the need for additional logic and latches as compared to prior techniques and to minimize additional globally routed signals. Additional commands decoded by TAP command processing provides desired specialized control for the enhanced boundary scan register.

Abstract: A semiconductor memory device includes at least one memory cell for storing digital data. A local sense amplifier is operably coupled to the at least one memory cell for receiving a first signal representative of the digital data stored in the at least one memory cell, and outputting a second signal representative of the received first signal in response to a first strobe signal. A global sense amplifier is operably coupled to the local sense amplifier for receiving the second signal, and outputting a third signal representative of the received second signal in response to a second strobe signal. Dummy circuitry is provided for-enabling generation of the first and second strobe signals.