Abstract: The electrostatic discharge protection apparatus includes a substrate, a first well having a first conductivity type and disposed in the substrate, a second well having a second conductivity type and disposed in the first well, a first doping region having the first conductivity type and disposed in the second well, a second doping region having the first conductivity type and disposed in the second well, a third doping region having the second conductivity type and disposed in the second well, and a fourth doping region having the first conductivity type and disposed in the substrate. The first conductivity type is different from the second conductivity type. The second well, the first well, the substrate and the fourth doping region form a silicon controlled rectifier. Electrostatic discharge current flowing into the first doping region flows to the fourth doping region through the silicon controlled rectifier.

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

Abstract: A memory device includes a stacked structure and at least one first element structure. The stacked structure is in a memory array region and a staircase contact region. The stacked structure includes first conductive layers and a second conductive layer arranged in a longitudinal direction. The memory array region and the staircase contact region are arranged in a first lateral direction. The at least one first element structure passes through the first conductive layers and the second conductive layer along the longitudinal direction. The first conductive layers surround a sidewall surface of the at least one first element structure. The second conductive layer includes conductive portions arranged in a second lateral direction. The conductive portions are completely separated from each other by the at least one first element structure. The first lateral direction is different from the second lateral direction.

Abstract: A memory device and an operation method thereof are provided. The operation method includes: when a read operation or a write-verify operation is completed, during a word line voltage lowering phase, synchronously applying a plurality of different gradually lowering signal line reference voltages to a plurality of ground select lines and a plurality of string select lines, wherein values of the different gradually lowering signal line reference voltages are corresponding to a plurality of signal line positions of the ground select lines and the string select lines.

Abstract: A semiconductor device includes a stack formed on a substrate and memory strings penetrating the stack along a first direction. The stack includes conductive layers and insulating layers that alternately stacked. Each of the memory strings includes a channel layer, a memory structure, a first conductive pillar and a second conductive pillar. The channel layer, the first conductive pillar and the second conductive pillar extend along a first direction. The memory structure is disposed between the stack and the channel layer. The first conductive pillar and the second conductive pillar are electrically isolated from each other, and are respectively coupled to a first portion and a second portion of the channel layer. The first portion is opposite to the second portion. The first portion is surrounded by the memory structure, and the second portion is exposed from the memory structure.

Abstract: The application provides a Content Addressable Memory (CAM) cell, a CAM memory device and an operation method thereof. The CAM cell includes: a plurality of parallel-coupled flash memory cells: wherein a storage data of the CAM cell is based on a combination of a plurality of threshold voltages of the parallel-coupled flash memory cells.

Abstract: A ternary content addressable memory, disposed in a stacked memory device, includes a first memory cell string and a second memory cell string. The first memory cell string is coupled between a matching line and a first source line and receives multiple first word line signals. The first memory cell string has a first memory cell string selection switch controlled by a first search signal. The second memory cell string is coupled between the matching line and a second source line and receives multiple second word line signals. The second memory cell string has a second memory cell string selection switch controlled by a second search signal.

Abstract: A three-dimension memory device, a memory circuit and a production method are provided. The three-dimension memory circuit includes a peripheral circuit, a metal layer, a buffer layer, a poly silicon layer, and a via array. The peripheral circuit is disposed on a substrate. The metal layer covers on the peripheral circuit and is electrically coupled to the peripheral circuit. The buffer layer is disposed on the metal layer. The poly silicon layer receives a reference ground voltage and is disposed on the buffer layer. The via array is disposed in the buffer layer and is used to electrically connect the metal layer and the poly silicon layer.

Abstract: The present disclosure provides a 3D memory structure such as 3D Flash memory structure applying for 3D AND flash memory and a method of forming the same. An etching stop layer is formed on a substrate including active elements. A stacked layer is formed on the etching stop layer. The stacked layer includes insulation layers and sacrificed layers stacked alternatively on the etching stop layer. A patterning process is performed on the stacked layer to form a first stacked structure above the active elements, a second stacked structure surrounding the first stacked structure, and a trench pattern separating the first stacked structure and the second stacked structure and exposing the etching stop layer. The trench pattern includes asymmetric inner sidewalls and outer sidewalls. The inner sidewalls define sidewalls of the first stacked structure. The outer sidewalls define sidewalls of the second stacked structure that face the first stacked structure.

Abstract: A memory device and a data approximation search method thereof are proposed. The memory device includes a plurality of selection switch pairs, a plurality of memory cell string pairs, a sense amplifier, and a page buffer. The selection switch pairs receive multiple search data pairs, respectively. The memory cell string pairs are respectively coupled to a global bit line through the selection switch pairs. Each of the memory cell string pairs determines whether to provide current on the global bit line according to stored data of a selected memory cell pair and each of the search data pairs. The sense amplifier obtains multiple search results according to the current on the global bit line and at least one reference currents respectively corresponding to at least one similarity. The page buffer records the search results and generates similarity information by accumulating the search results.

Abstract: Methods, systems and apparatus for memory devices with discharging circuits are provided. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharging circuits arranged on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharging circuits, and a memory array having a three-dimensional (3D) array of memory cells arranged in a plurality of vertical channels on the one or more CSL layers. Each of the plurality of vertical channels includes a respective string of memory cells, and each of the one or more CSL layers is conductively coupled to corresponding strings of memory cells. Each of the one or more discharging circuits includes one or more transistors that are disabled by one or more corresponding conductive lines through the memory array.

Abstract: A memory device, for executing an anneal computation with first state and a second state. The memory device includes a first memory array, a second memory array, a control circuit, a sensing circuit and a processing circuit. the control circuit selects a first horizontal row of memory units from the first memory array, and selects a second horizontal row of memory units from the second memory array. The sensing circuit computes a local energy value of the first state according to the current generated by the memory units of the first horizontal row, and computes a local energy value of the second state according to the current generated by the memory units of the second horizontal row. The processing circuit updates the first state and/or the second state according to the local energy value of the first state and the local energy value of the second state.

Abstract: A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.

Abstract: A memory device may be applicated in a 3D AND flash memory device. The memory device includes a gate stack structure, a doped channel stack structure, a source pillar and a drain pillar, and a plurality of dielectric structures. The gate stack structure is located on a substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The doped channel stack structure extends through the gate stack structure. The doped channel stack structure includes a plurality of doped channel rings spaced apart from each other. The source pillar and the drain pillar extend through the doped channel stack structure. The source pillar and the drain pillar are respectively electrically connected to the plurality of doped channel rings. The plurality of dielectric structures are located between the plurality of gate layers and the plurality of doped channel rings.

Abstract: A memory device may be applicated in a 3D AND flash memory device. The memory device includes a dielectric substrate, a plurality of memory cells, a slit structure, and a middle section of a seal ring. The gate composite stack structure disposed on the dielectric substrate in a first region and a second region of the dielectric substrate. The plurality of memory cells disposed in the composite stack structure. The slit structure extends through the composite stack structure in first region. The composite stack structure is divided into a plurality of blocks. The middle section of a seal ring extends through the composite stack structure in the second region. The middle section of the seal ring includes a body part extending through the composite stack structure in the second region and a liner layer located between the body part and the composite stack structure.

Abstract: A semiconductor device may be applicated in a three-dimensional AND flash memory device. The semiconductor device includes a dielectric substrate, a composite stack structure, a vertical pillar array and a resistor. The dielectric substrate includes a first region and a second region. The composite stack structure is located over the dielectric substrate in the first region and the second region. The vertical pillar array is disposed in the composite stack structure in the first region. The resistor is laterally adjacent to the vertical pillar array, extends below the composite stack structure in the second region, extends through the composite stack structure, and extends above the composite stack structure.

Abstract: A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.

Abstract: A memory device is provided that includes a memory array including a first array, a first redundant array that is local to the first array, a second array, and a second redundant array that is local to the second array, a cache array including a first cache, a first redundant cache that is local to the first cache, a second cache and a second redundant cache that is local to the second cache, and circuits comprising logic to execute operations. The operations include, responsive to an identification of a defective column in the first array, performing a local defect write repair and responsive to an identification of another defective column in the first array and a determination that the first redundant array is fully utilized, performing a global defect write repair by transferring data into the second redundant array through the first cache and the second redundant cache.