Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

Abstract: A switch control circuit and a switch control method are provided. In this circuit, compositions that sense a drain voltage of a switch device are added in a QR Buck Converter switch control circuit. A first resistor, a second switch, a second resistor are electrically connected to a drain terminal of a switch device to sense the 0 A state of an inductor current. On the basis of a detection result, the switch control circuit turns on the switch device when an inductor current is 0 A, and a drain sensing voltage (ZCD) is less than a predetermined reference voltage (REF).

Abstract: A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.

Abstract: A multi-vision display device includes a timing controller, a plurality of display panels, and a plurality of display driver integrated circuits (ICs). The timing controller is configured to receive source data and timing signals from a host, and generate a data packet comprising image data and control data. The plurality of display driver ICs each is connected to any one of the plurality of display panels. The control data includes a panel identifier indicating a number of display panels of the plurality of display panels connected to the display driver IC prior to a corresponding display panel connected to the display driver IC. Adjacent ones of the plurality of display driver ICs are connected to each other, modulate the panel identifier provided from one among the timing controller and a front end display driver IC, and provide the modulated panel identifier to a rear end display driver IC.

Abstract: An image processing apparatus includes: a line buffer configured to store image data; a clock gating circuit configured to apply a clock signal to the line buffer; and a data processor configured to determine, when performing a write operation, whether to skip the write operation to the line buffer for each of adjacent data according to whether a value of each of the adjacent data within an image is the same, wherein the data processor is further configured to control the clock gating circuit, such that the clock signal is prevented from being applied to the line buffer while the write operation is skipped and the clock signal is applied to the line buffer while the write operation is performed.

Abstract: A display device includes: a display panel including a plurality of pixels, a driver integrated circuit (IC) configured to convert digital data corresponding to an input image to an analog data voltage using a gamma voltage, and to supply the analog data voltage to the plurality of pixels, and a power supply configured to supply a pixel driving voltage to the display panel and the driver IC, and the driver IC includes: a weight selector configured to select a weight for adjusting the gamma voltage based on an amount of change in the pixel driving voltage supplied from the power supply, and a gamma reference voltage generating circuit configured to generate a gamma reference voltage based on the selected weight.

Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: A power semiconductor device includes: a drain electrode; a first conductive substrate disposed on the drain electrode; a first conductive epitaxial layer disposed on the first conductive substrate; a first conductive drift layer formed within the first conductive epitaxial layer; trenches formed in the first conductive epitaxial layer; a shield electrode formed in a lower portion of each trench; a shield oxide layer formed within each trench and formed to surround the shield electrode; a gate electrode formed within each trench and formed on the shield electrode; a second conductive body region formed on an upper portion comprising a surface of the first conductive epitaxial layer between the plurality of trenches; a source region formed on the second conductive body region; an insulation layer formed on the gate electrode; a source contact layer formed in contact with the source region; and a source electrode formed on the source contact layer.

Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

Abstract: A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region.

Abstract: A mask layout for forming a semiconductor device includes an active mask pattern, a gate electrode mask pattern, a silicide blocking mask pattern, and a contact mask pattern. The active mask pattern forms source and drain regions in a substrate. The gate electrode mask pattern, disposed to overlap the active mask pattern, forms a gate electrode between the source region and the drain region. The silicide blocking mask pattern is disposed to overlap the gate electrode mask pattern and the active mask pattern in the gate electrode, the source region, and the drain regions to form a silicide blocking region. The contact mask pattern, disposed spaced apart from the silicide blocking mask pattern, forms a contact plug on the substrate. The silicide blocking mask pattern covers the gate electrode mask pattern and extends to the active mask pattern.

Abstract: A power factor correction circuit includes an inductor configured to receive an input voltage and supply an output voltage; a power switch connected to the inductor and configured to control an input current flowing through the inductor; and a switch controller configured to receive a feedback voltage including information on the output voltage and an auxiliary voltage including information on a voltage of the inductor and control an on/off operation of the power switch. The switch controller is further configured to operate in a first mode when the feedback voltage is less than a reference voltage, and operate in a second mode when the feedback voltage is greater than the reference voltage.

Abstract: A wafer level chip scale package includes a semiconductor substrate having a first thickness, an input-output pad formed on the semiconductor substrate, a front metal layer having a second thickness formed on the input-output pad, a back metal layer having a third thickness formed on a bottom of the semiconductor substrate, and a metal bump formed on the semiconductor substrate.

Abstract: A source driver for a display panel includes an output buffer configured to output a signal to a data line of the display panel; an output controller configured to control an output of the output buffer; a load resistance measuring unit configured to measure a load resistance of at least one data line of the display panel; and a comparison unit configured to compare the load resistance measured in the load resistance measuring unit with an initial load resistance, wherein the output controller is further configured to control a signal to be output by the output buffer based on the comparison result.

Abstract: A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.

Abstract: A current generating circuit includes a current generator configured to supply a reference current, switches connected to the current generator, wherein one switch of the switches is selected and configured to operate, according to a switch selection signal, and one or more resistors, respectively connected to the switches, wherein a rate of current change according to a temperature change of the current generator is adjusted based on a temperature coefficient of resistance (TCR) of resistors connected to the one switch, according to adjustment of the one switch.

Abstract: A switch control circuit and a switch control method are provided. The switch control circuit includes a load, an inductor, a control switch, and a sensing resistance connected in series to an input power source; an integrator that integrates a sensing voltage and a load current setting voltage to generate an integrated signal; a comparator that compares the integrated signal and a bias voltage; a switch driver that controls the control switch based on an output of the comparator and an output of an off time controller; and a gate sensor that outputs, to the integrator, a gate sensing signal that senses a time when an input of a gate terminal of the control switch becomes a low level. An integration operation is started from a position in which the integrated signal is located lower than the bias voltage, when an input of the gate terminal becomes a high level.

Abstract: A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.

Abstract: A low voltage drop output regulator and a method for controlling thereof for preventing an inrush current that occurs momentarily during an initial operation of a circuit are described. The low voltage drop output regulator includes a differential amplifier configured to output an amplified voltage by comparing a reference voltage with a feedback voltage, a first MOS transistor configured to output an output voltage to a drain terminal by receiving the amplified voltage in a gate terminal, and an inrush preventer connected between a power voltage terminal and a drive node to prevent the inrush current of the first MOS transistor during an initial operation period. The inrush preventer includes a determining unit and a limiter, and the limiter is configured only by a MOS transistor and a switch connected in series between a power voltage terminal and a drive node.