Patents Assigned to Magnachip Semiconductor, Ltd.
  • Patent number: 10431530
    Abstract: A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: October 1, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Si Hyeon Go, Jun Young Heo, Moon Taek Sung, Dong Seong Oh
  • Publication number: 20190288066
    Abstract: A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.
    Type: Application
    Filed: August 3, 2018
    Publication date: September 19, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Tae Hoon LEE, Jun Hee CHO, Jin Seong CHUNG
  • Patent number: 10418120
    Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier. The sense amplifier is connected to the bit line, receives a first control signal, and detects and amplifies a bit line signal of the bit line. The sense amplifier includes a precharge device that is turned on or turned off based on a read control signal, and a transistor output unit that outputs an output voltage based on the bit line signal when the precharge device is turned off.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 17, 2019
    Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Duk Ju Jeong
  • Patent number: 10411590
    Abstract: Provided is a power consumption reduction type power converter. For example, such a power converter includes a regulator configured to convert a power voltage into an operation power of a main integrated circuit (IC), a mode detecting pin configured to detect a voltage level of the operation power, wherein the detected voltage level indicates a disable mode or an enable mode, a mode signal output circuit connected to the mode detecting pin, configured to output a mode converting signal, and a switching controller configured to block or connect a power route according to the mode converting signal to supply or block the operation power from being provided to the main IC, wherein the mode detecting pin is connected to a first switch and a first capacitor to perform a charging or a discharging operation of the first capacitor according to a switching operation of the first switch.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 10, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Zhi Yuan Cui, In Ho Hwang, Young Gi Ryu, Tae Young Park, Sang Hoon Jeong
  • Patent number: 10395972
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: August 27, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Da Soon Lee, Hyung Suk Choi, Jeong Gyu Park, Gil Ho Lee, Hyun Tae Jung, Meng An Jung, Woo Sig Min, Pil Seung Kang
  • Publication number: 20190251925
    Abstract: A light emitting diode (LED) driving circuit that sequentially drive a plurality of series-coupled LED groups comprising at least one LED is provided. The LED driving circuit includes a plurality of mid nodes coupled to terminals of the plurality of the LED groups, a common node with a reference voltage, a switch unit configured to form a plurality of current movement paths between the common node and the plurality of the mid nodes and configured to select a current movement path based on a control signal, a current measuring unit configured to detect a current flow through the common node, and a current control unit configured to generate the control signal based on the detected current flow.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Hyun-jung KIM, Seung-hwan LEE
  • Patent number: 10381460
    Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: August 13, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Yu Shin Ryu, Bo Seok Oh, Jin Yeong Son
  • Publication number: 20190244833
    Abstract: A method for manufacturing a heat releasing semiconductor chip package includes attaching a first surface of a semiconductor chip onto an insulating film, injecting a coating liquid onto a second surface of the semiconductor chip to form a liquefied coating layer and curing the liquefied coating layer to form a heat releasing layer. The coating liquid includes a liquefied molding compound for heat releasing and fine alumina particles. Therefore, the heat releasing semiconductor chip package and method for manufacturing the semiconductor chip package form a heat releasing layer in direct contact with the semiconductor chip to maximize a heat releasing effect.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Jo Han KIM, Hee Jin PARK, Kyeong Su KIM, Jae Jin LEE
  • Patent number: 10373965
    Abstract: An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 6, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Young Chul Seo, Duk Ju Jeong
  • Publication number: 20190237544
    Abstract: A method for manufacturing a power semiconductor device includes forming a trench in a semiconductor substrate, forming a gate insulation film and a gate electrode in the trench, implanting a first conductivity type impurity into the semiconductor substrate to form a first conductivity type body region, implanting a second conductivity type impurity onto a surface of the semiconductor substrate to form a second conductivity type source region, forming an interlayer insulation film in the trench, implanting the first conductivity type impurity onto the surface of the semiconductor substrate to form a first conductivity type highly doped body contact region, exposing a portion of a side surface of the trench, and forming a source metal to be in contact with the exposed side surface of the trench.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 1, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Seong Jo HONG, Soo Chang KANG, Ha Yong YANG, Young Ho SEO
  • Publication number: 20190237140
    Abstract: A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.
    Type: Application
    Filed: September 6, 2018
    Publication date: August 1, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Su Jin KIM, Myeong Seok KIM, In Chul JUNG, Young Bae KIM, Seung Guk KIM, Jung Hwan LEE
  • Publication number: 20190229685
    Abstract: A semiconductor device includes a substrate comprising a WELL region, a gate electrode comprising a gate length disposed on the WELL region, and first and second drift regions which overlap with the gate electrode. The first and second draft regions may overlap with the gate electrode at an overlapping length which is a percentage of the gate length.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 25, 2019
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Hee Hwan JI, Tae Ho KIM
  • Patent number: 10361163
    Abstract: A circuit for preventing forgery of semiconductor chip includes a driving signal protection unit and a control unit. The driving signal protection unit configured to include at least one protection wire protecting a driving wire having driving signals flow therethrough. The control unit configured to generate a first security code and a second security code. The control unit is further configured to compare the first security code that passes through the driving signal protection unit and the second security code that bypasses the driving signal protection unit to detect tampering at the at least one protection wire, and to control operation of the semiconductor chip.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 23, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Yong Sup Lee
  • Patent number: 10347565
    Abstract: A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 9, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Si Hyeon Go, Jae Sik Choi, Myung Ho Park, Dong Seong Oh, Beom Su Kim
  • Publication number: 20190207005
    Abstract: The description relates to a semiconductor die having a stacking structure of silicon-metallic conductive layer-silicon, and the semiconductor die according to embodiments includes a stacking structure of first semiconductor layer-metallic conductive layer-second semiconductor layer, and first and second power semiconductor devices in the first semiconductor layer, in which the first power semiconductor device includes a first source bump and a first gate bump, first trench gate electrodes under the first source bump, and a first channel among the plurality of first trench gate electrodes, in which the second power semiconductor device includes a second source bump and a second gate bump, second trench gate electrodes under the second source bump, and a second channel among the plurality of second trench gate electrodes, and in which the metallic conductive layer includes a metal layer.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 4, 2019
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Myung Ho PARK, Ul Kyu SEO, Young Ho SEO, Jae Sik CHOI
  • Patent number: 10340156
    Abstract: A method for manufacturing a heat releasing semiconductor chip package includes attaching a first surface of a semiconductor chip onto an insulating film, injecting a coating liquid onto a second surface of the semiconductor chip to form a liquefied coating layer and curing the liquefied coating layer to form a heat releasing layer. The coating liquid includes a liquefied molding compound for heat releasing and fine alumina particles. Therefore, the heat releasing semiconductor chip package and method for manufacturing the semiconductor chip package form a heat releasing layer in direct contact with the semiconductor chip to maximize a heat releasing effect.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 2, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jo Han Kim, Hee Jin Park, Kyeong Su Kim, Jae Jin Lee
  • Patent number: 10339888
    Abstract: A light emitting diode (LED) driving circuit that sequentially drive a plurality of series-coupled LED groups comprising at least one LED is provided. The LED driving circuit includes a plurality of mid nodes coupled to terminals of the plurality of the LED groups, a common node with a reference voltage, a switch unit configured to form a plurality of current movement paths between the common node and the plurality of the mid nodes and configured to select a current movement path based on a control signal, a current measuring unit configured to detect a current flow through the common node, and a current control unit configured to generate the control signal based on the detected current flow.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: July 2, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Hyun-jung Kim, Seung-hwan Lee
  • Publication number: 20190198415
    Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.
    Type: Application
    Filed: March 6, 2019
    Publication date: June 27, 2019
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik CHOI, Dong Seong OH, Si Hyeon GO
  • Publication number: 20190198682
    Abstract: A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Yong Won LEE, Jin Woo HAN, Dae Won HWANG, Kyung Wook KIM
  • Publication number: 20190199191
    Abstract: A high voltage start-up circuit includes a power supply terminal configured to supply power, a latch unit connected to the power supply terminal and comprising a first P-type Metal-Oxide-Semiconductor (PMOS) transistor, a first N-type metal-oxide semiconductor (NMOS) transistor connected to the first PMOS transistor, a second PMOS transistor, and a second NMOS transistor connected to the second PMOS transistor, wherein the transistors form a latch structure, a charge sharing unit comprising a first capacitor configured to supply a first voltage to a drain of the second PMOS transistor and a second capacitor configured to supply a second voltage to a drain of the first PMOS transistor, and a switching unit configured to form a current path that charges an external capacitor using a voltage supplied from the power supply terminal as a power voltage, based on the first voltage and the second voltage.
    Type: Application
    Filed: August 23, 2018
    Publication date: June 27, 2019
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Zhi Yuan CUI, Sang Hoon JUNG, Dong Seong OH, Byung Ki KIM