Patents Assigned to Magnachip Semiconductor, Ltd.
  • Patent number: 11011092
    Abstract: A decoder of a display apparatus and a decoding method thereof is provided. The decoder comprises a first switching control block configured to select at least two section values from a plurality of gamma gray level values based on predetermined low bits of inputted data, and a second switching control block configured to select section values from the at least two selected section values based on predetermined high bits of the data and output at least two channel values.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 18, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Eun Kyu Seong
  • Patent number: 11011445
    Abstract: A semiconductor package device includes a lead frame including a lead frame pad and lead frame leads, a semiconductor chip located on the lead frame pad, and a substrate located on the semiconductor chip, wherein the lead frame leads include first lead frame leads coupled to the lead frame pad and second lead frame leads separated from the lead frame pad and attached to a bottom surface of the substrate.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 18, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Moon Taek Sung, Jae Sik Choi
  • Patent number: 10991637
    Abstract: A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 27, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Myung Ho Park, Beom Su Kim, Sun Hwan Kim
  • Patent number: 10943666
    Abstract: A power switch circuit comprises a first level shifter configured to turn on a first switching element configured to receive a supply voltage from an external voltage supply pad in response to a program operation of a one-time programmable (OTP) memory cell array, a second level shifter configured to turn on a second switching element and provide the supply voltage to the OTP memory cell array in response to the program operation, a third level shifter configured to turn on a third switching element and provide an internally generated power voltage to the OTP memory cell array in response to a read operation of the OTP memory cell array, and an Electro-Static Discharge (ESD) protection circuit configured to turn off the first switching element in response to a flow of ESD voltage from the voltage supply pad.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 9, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Duk Ju Jeong
  • Patent number: 10943559
    Abstract: A display driver IC includes a register map, an oscillator, a timing controller, an oscillator scatter, and an intellectual property (IP) block. The register map is configured to store a trim code of a fixed frequency and scatter option information. The oscillator is configured to generate an oscillator clock based on the trim code. The timing controller is configured to generate an internal synchronization signal based on the oscillator clock. The oscillator scatter is configured to output a modified trim code to the oscillator based on the trim code, the scatter option information, and the internal synchronization signal. The intellectual property (IP) block is configured to receive a modified oscillator clock generated in the oscillator based on the modified trim code.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: March 9, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Sang Su Park
  • Publication number: 20210051785
    Abstract: A switching driving circuit includes a switch configured to switch a current supplied to a target circuit, a sensing resistor connected to the switch, a controller configured to control the switch by comparing a sensing voltage applied to the sensing resistor with a reference voltage, and a compensation circuit configured to regulate the reference voltage based on an amount of variation of an input voltage input into the target circuit and an output voltage output from the target circuit.
    Type: Application
    Filed: April 15, 2020
    Publication date: February 18, 2021
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jang Hyuck LEE, Joo Han YOON, Byoung Kwon AN
  • Patent number: 10910270
    Abstract: A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer which has a seal-ring region, forms a first interlayer insulating film on the wafer, forms a metal wiring in the first interlayer insulating film, forms a second interlayer insulating film on the first interlayer insulating film, forms metal pads on the second interlayer insulating film, forms a passivation layer on the metal pads, removes a portion of the passivation layer in a region adjacent to the seal-ring region to expose the second interlayer insulating film, etches a portion of the second interlayer insulating film, forms a bump on the metal pads, removes the first interlayer insulating film and the second interlayer insulating film in the region adjacent to the seal-ring region by a laser grooving process, and dices the wafer into a first semiconductor die and a second semiconductor die.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: February 2, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Jin Won Jeong, Byeung Soo Song, Dong Ki Shim, Jin Han Bae
  • Publication number: 20210026385
    Abstract: A low dropout voltage regulator includes a differential amplifier configured to output an amplified voltage by comparing a feedback voltage with a reference voltage, a pass transistor configured to receive a power input voltage into a source terminal, the amplified voltage into a gate terminal, and output an output voltage into a drain terminal, distribution resistors connected between the drain terminal and the ground terminal, configured to generate the feedback voltage, and an inrush preventer, connected in parallel between the differential amplifier and the pass transistor, and configured to output a regulated amplified voltage into the gate terminal according to a control signal, wherein the inrush preventer comprises a determiner configured to output an enable signal that is turned on during an initial driving period, and a limiter configured to output the regulated amplified voltage according to the enable signal.
    Type: Application
    Filed: April 22, 2020
    Publication date: January 28, 2021
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Ju Sang PARK, Hyung Sun KIM, Hyoung Kyu KIM
  • Publication number: 20210021191
    Abstract: An integration circuit is provided. The integration circuit includes a current source, a capacitor connected in series with the current source, a voltage source bias connected in series with the capacitor, a switch configured to connect a first node between the current source and the capacitor and a second node between the capacitor and the voltage source bias; and a switch control logic unit configured to control an on/off operation of the switch, wherein an integration operation is performed by the current source and the capacitor.
    Type: Application
    Filed: March 26, 2020
    Publication date: January 21, 2021
    Applicant: MagnaChip Semiconductor Ltd.
    Inventors: Jang Hyuck LEE, Joo Han YOON, Byoung Kwon AN, Jay LEE
  • Patent number: 10891914
    Abstract: A control buffer in a source driver includes a first CMOS inverter configured to output a switch signal to control turning on and off of a switch, and a first tri-state inverter that is connected to the first CMOS inverter and configured to selectively adjust a size of the control buffer, wherein a slew rate of the switch signal is adjusted depending on the size of the control buffer.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 12, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Eun Kyu Seong, Hyoung Kyu Kim
  • Publication number: 20210005169
    Abstract: A device for driving a display panel includes a display driving integrated circuit (IC) configured to transmit image data to the display panel, a display control IC configured to receive compressed image data from a host and including a timing controller configured to control the display driving IC, and a non-volatile memory configured to transmit data to and receive data from the display control IC, and configured to store driving parameters necessary for operation of the display driving IC.
    Type: Application
    Filed: April 28, 2020
    Publication date: January 7, 2021
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Seok YANG, Jung Hoon SUL, Sang Kyung KIM, Dae Young YOO, Jae Won KIM
  • Publication number: 20200394981
    Abstract: A gamma correction circuit includes an input circuit configured to sequentially receive gamma control signals used for selecting gamma tap points from a control circuit through a single transmission line, and to output the received gamma control signals, and a voltage generator configured to select the gamma tap points based on the gamma control signals, and to generate gamma voltages according to the gamma tap points.
    Type: Application
    Filed: March 27, 2020
    Publication date: December 17, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Myung Woo LEE, Hee Sung YANG
  • Publication number: 20200389165
    Abstract: A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.
    Type: Application
    Filed: March 26, 2020
    Publication date: December 10, 2020
    Applicant: Magnachip Semiconductor, Ltd.
    Inventors: Jung Hoon SUL, Dong Il SEO
  • Publication number: 20200381445
    Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Su Jin KIM, Hye Jin YOO
  • Publication number: 20200373293
    Abstract: A semiconductor device includes a P-type substrate, a P-type well region, an N-type well region, an N-type guard ring region, an insulating layer, a poly gate disposed, and a bulk region. The P-type well region is disposed on the P-type substrate and includes source regions and drain regions each spaced apart from the other. The N-type well region disposed and spaced apart from the P-type well region on the P-type substrate. The N-type guard ring region is disposed around perimeters of the P-type well region and the N-type well region. The insulating layer is disposed around the P-type well region and the N-type well region on the N-type guard ring region. The poly gate is disposed around the perimeter of the P-type well region and the N-type well region, respectively, on the insulating layer. The bulk region is disposed on the N-type guard ring region adjacent the poly gate.
    Type: Application
    Filed: November 13, 2019
    Publication date: November 26, 2020
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Won Jong BAEK
  • Patent number: 10833095
    Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 10, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Su Jin Kim, Hye Jin Yoo
  • Publication number: 20200343145
    Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.
    Type: Application
    Filed: September 4, 2019
    Publication date: October 29, 2020
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Yang Beom KANG, Kang Sup SHIN
  • Patent number: 10809318
    Abstract: There is provided a hall sensor. The hall sensor includes a hall element disposed on a semiconductor substrate. The hall element includes: a sensing region, a first electrode, a second electrode, a third electrode and a fourth electrode, and a doped region disposed on the sensing region, and the sensing region has at least one angulated corner or rounded corner.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: October 20, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Seong Woo Lee, Hee Baeg An
  • Patent number: 10796661
    Abstract: A display driver IC which adjusts an oscillator frequency is provided. The display driver IC includes: a register map which stores a trim code, a window size, compensation information, and a compensation option; an oscillator which generates an oscillator clock based on the trim code; a timing controller which generates an internal synchronization signal based on the oscillator clock; a DSI block which outputs a first data valid signal which is activated based on a data clock and image data packet update; and a frequency compensating block which compares a periodic value of the oscillator clock calculated based on the data clock and the internal synchronization signal with a target periodic value and generates a compensation trim code obtained by compensating the trim code based on the compensation option, in accordance with the first data valid signal.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 6, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Sang Su Park
  • Publication number: 20200312715
    Abstract: A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer which has a seal-ring region, forms a first interlayer insulating film on the wafer, forms a metal wiring in the first interlayer insulating film, forms a second interlayer insulating film on the first interlayer insulating film, forms metal pads on the second interlayer insulating film, forms a passivation layer on the metal pads, removes a portion of the passivation layer in a region adjacent to the seal-ring region to expose the second interlayer insulating film, etches a portion of the second interlayer insulating film, forms a bump on the metal pads, removes the first interlayer insulating film and the second interlayer insulating film in the region adjacent to the seal-ring region by a laser grooving process, and dices the wafer into a first semiconductor die and a second semiconductor die.
    Type: Application
    Filed: July 30, 2019
    Publication date: October 1, 2020
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik CHOI, Jin Won JEONG, Byeung Soo SONG, Dong Ki SHIM, Jin Han BAE