Patents Assigned to Matsushita Electronics Corporation
  • Publication number: 20080038856
    Abstract: The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in Schottky contact with the active region extending onto the insulating oxide film and having an extended portion on the insulating oxide film is formed, and ohmic electrodes respectively serving as a source electrode and a drain electrode are formed with space from side edges along the gate length direction of the gate electrode.
    Type: Application
    Filed: September 18, 2007
    Publication date: February 14, 2008
    Applicant: Matsushita Electronics Corporation
    Inventors: Katsunori NISHII, Kaoru INOUE, Toshinobu MATSUNO, Yoshito IKEDA, Hiroyuki MASATO
  • Publication number: 20060065918
    Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.
    Type: Application
    Filed: November 10, 2005
    Publication date: March 30, 2006
    Applicant: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Yasuhiro Uemoto
  • Publication number: 20050045990
    Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 3, 2005
    Applicant: Matsushita Electronics Corporation
    Inventors: Keisaku Nakao, Akihiro Matsuda, Yasufumi Izutsu, Toyoji Ito, Takumi Mikawa, Toru Nasu, Yoshihisa Nagano, Keisuke Tanaka, Toshie Kutsunai
  • Patent number: 6822493
    Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: November 23, 2004
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroshige Hirano, Kouji Asari, Tatsumi Sumi
  • Patent number: 6734633
    Abstract: In a bulb-form lamp, a threaded portion 31 of a lamp cap 5, that is, a shell 30 is made of a conductive resin. The conductive resin shell 30 and an eyelet 50 constituting the lamp cap 5 are composite parts, which are molded integrally with a lamp case 20. A part of the conductive resin shell 30 is provided with a terminal connective portion 30a projecting into the lamp case 20. The terminal connective portion 30a is connected with an electrode terminal 40 led out of a printed circuit board 13 of a lighting circuit 14 so that the conductive resin shell 30 and the lighting circuit 14 are electrically connected. By doing so, it is possible to simplify the assembly of bulb-form lamp, and to reduce an assembly cost, and further, to manufacture a bulb-form lamp having a high quality and a lamp case for the bulb-form lamp.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: May 11, 2004
    Assignees: Matsushita Electronics Corporation, Shinsei Kagaku Kogyo Co., Ltd.
    Inventors: Tetsuo Matsuba, Shinichiro Ishitsuka, Masato Kawase, Tsuneo Miyata, Tomotaka Arikawa, Takenori Shibata, Haruyuki Hirokawa
  • Patent number: 6677195
    Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: January 13, 2004
    Assignee: Matsushita Electronics Corporation
    Inventor: Katsuhiko Tsuura
  • Patent number: 6671301
    Abstract: A semiconductor laser device including: a semiconductor substrate of a first conductivity type; a cladding layer of the first conductivity type provided on the semiconductor substrate; an active layer provided on the cladding layer of the first conductivity type, the active layer having a super-lattice structure including a disordered region in a vicinity of at least one cavity end face; a first cladding layer of a second conductivity type provided on the active layer; an etching stop layer of the second conductivity type provided on the first cladding layer; and a second cladding layer of the second conductivity type provided on the etching stop layer, the second cladding layer forming a ridge structure, the ridge structure extending along a cavity length direction and having a predetermined width.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: December 30, 2003
    Assignee: Matsushita Electronics Corporation
    Inventors: Toshikazu Onishi, Hideto Adachi, Masaya Mannou, Akira Takamori
  • Patent number: 6667216
    Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: December 23, 2003
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroyuki Umimoto, Shinji Odanaka
  • Publication number: 20030207470
    Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.
    Type: Application
    Filed: July 5, 2001
    Publication date: November 6, 2003
    Applicants: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Masamichi Azuma, Carlos A. Paz De Araujo
  • Patent number: 6630629
    Abstract: Signal wirings 22, 23 are formed on a pair of substrates 20, 21, and the substrates are joined together through an insulating layer 24 so that the signal wirings 22, 23 are placed in parallel and facing to each other. The surfaces of the overlapping faces of the signal wirings 22, 23 are made smooth, and the roughness of the same surfaces is smaller than the skin depth &dgr;s due to the skin effect, preferably less than one third, for minimizing the increase in the electric resistance due to the skin effect.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: October 7, 2003
    Assignees: Sanyo Electric Co., Ltd., Oki Electric Industry Co., Ltd., Sharp Kabushiki Kaisha, Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Hitachi, Ltd., Fujitsu Limited, Matsushita Electronics Corporation, Mitsubishi Denki Kabushiki Kaisha, Rohm Co., Ltd.
    Inventors: Kanji Otsuka, Tamotsu Usami
  • Patent number: 6620738
    Abstract: An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH4F and H2O. When the etchant has a NH4F/HCl molar ratio of less than one, only the titanium material is etched. When the etchant has a NH4F/HCl molar ratio of more than one, only silicon oxide is etched. When the etchant has a NH4F/HCl molar ratio of one, the titanium material and silicon oxide are etched at the same rate.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 16, 2003
    Assignee: Matsushita Electronics Corporation
    Inventors: Hidetoshi Ishida, Atsushi Noma, Daisuke Ueda
  • Publication number: 20030155621
    Abstract: After an insulating film serving as a gate insulating film is formed on a semiconductor substrate, a titanium nitride film is deposited by chemical vapor deposition on the insulating film. Then, a tungsten film is deposited by sputtering on the titanium nitride film. Subsequently, a multilayer film composed of the tungsten film and the titanium nitride film is patterned to form a gate electrode composed of the multilayer film.
    Type: Application
    Filed: February 24, 2003
    Publication date: August 21, 2003
    Applicant: MATSUSHITA ELECTRONICS CORPORATION
    Inventors: Masaru Moriwaki, Takayuki Yamada, Kazuhiko Yamamoto
  • Publication number: 20030141554
    Abstract: A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.
    Type: Application
    Filed: February 3, 2003
    Publication date: July 31, 2003
    Applicant: MATSUSHITA ELECTRONICS CORPORATION
    Inventors: Takashi Uehara, Masato Kanazawa
  • Patent number: 6594598
    Abstract: In a production line for obtaining a final product by performing a plurality of process steps on each of a plurality of products, when one of the process steps is finished, measured data is obtained by measuring the characteristics of a product on which the process step has been performed. Based on the measured data obtained, the performance of a final product is expected. And based on the expected performance of the final product, the number of products estimatingly finished for each performance rank thereof is calculated.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: July 15, 2003
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroaki Ishizuka, Kyoji Yamashita
  • Patent number: 6590918
    Abstract: A method for producing a semiconductor laser element includes steps of: forming a semiconductor layered structure on a first conductivity type semiconductor substrate, the semiconductor layered structure including a first conductivity type cladding layer, a quantum well active layer, and a first cladding layer of a second conductivity type; forming a diffusion control layer in a predetermined region on the semiconductor layered structure; forming a material layer which acts as an impurity source on the diffusion control layer; and diffusing impurities by a first thermal treatment from the material layer through the diffusion control layer into at least a part of the semiconductor layered structure including at least a part of the quantum well active layer, thereby forming an impurity diffusion region, wherein a part of the quantum well active layer in at least one cavity end face is disordered by diffusion of the impurities.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: July 8, 2003
    Assignee: Matsushita Electronics Corporation
    Inventors: Masaya Mannou, Toshiya Fukuhisa
  • Patent number: 6582972
    Abstract: A thin film of precursor for forming a layered superlattice material is applied to an integrated circuit substrate, then a strong oxidizing agent is applied at low temperature in a range of from 100° C. to 300° C. to the precursor thin film, thereby forming a metal oxide thin film. The strong oxidizing agent may be liquid or gaseous. An example of a liquid strong oxidizing agent is hydrogen peroxide. An example of a gaseous strong oxidizing agent is ozone. The metal oxide thin film is crystallized by annealing at elevated temperature in a range of from 500° C. to 700° C., preferably not exceeding 650° C., for a time period in a range of from 30 minutes to two hours. Annealing is conducted in an oxygen-containing atmosphere, preferably including water vapor. Treatment by ultraviolet (UV) radiation may precede annealing. RTP in a range of from 500° C. to 700° C. may precede annealing.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: June 24, 2003
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Vikram Joshi, Jolanta Celinska, Narayan Solayappan, Larry D. McMillan, Carlos A. Paz de Araujo, Koji Arita
  • Publication number: 20030109088
    Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 12, 2003
    Applicant: Matsushita Electronics Corporation
    Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
  • Patent number: 6573111
    Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mate
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: June 3, 2003
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Yasuhiro Uemoto, Yuji Judai, Masamichi Azuma, Eiji Fujii
  • Publication number: 20030094698
    Abstract: A fluorine-containing organic film having a relative dielectric constant of 4 or less is deposited on a semiconductor substrate using a material gas containing fluorocarbon as a main component in a reactor chamber of a plasma processing apparatus. During the deposition of the fluorine-containing organic film, a scavenger gas for scavenging fluorine constituting the fluorocarbon is mixed in the material gas. The proportion of the mixed scavenger gas in the material gas is changed to adjust the mechanical strength and relative dielectric constant of the fluorine-containing organic film.
    Type: Application
    Filed: December 30, 2002
    Publication date: May 22, 2003
    Applicant: Matsushita Electronics Corporation
    Inventors: Nobuhiro Jiwari, Shinichi Imai
  • Patent number: 6563140
    Abstract: A semiconductor light emitting device of the present invention includes: a substrate; a light emitting layer; a semiconductor layer of a hexagonal first III-group nitride crystal; and a cladding layer of a second III-group nitride crystal. A stripe groove is provided in the semiconductor layer along a <1, 1, −2, 0> direction.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: May 13, 2003
    Assignee: Matsushita Electronics Corporation
    Inventors: Shinji Nakamura, Masahiro Ishida, Masaaki Yuri, Osamu Imafuji, Kenji Orita