Patents Assigned to Megica Corporation
  • Publication number: 20140021522
    Abstract: Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 23, 2014
    Applicant: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20140021630
    Abstract: In the present invention, discrete decoupling capacitors are mounted on the surface of an IC chip. Since a discrete capacitor can provide the capacitance of the magnitude ?F, the attached capacitors can serve as the local power reservoir to decouple the external power ground noise caused by wirebonds, packages, and other system components.
    Type: Application
    Filed: January 7, 2013
    Publication date: January 23, 2014
    Applicant: Megica Corporation
    Inventor: Mou-Shiung Lin
  • Publication number: 20130309812
    Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 21, 2013
    Applicant: MEGICA CORPORATION
    Inventor: Megica Corporation
  • Patent number: 8558383
    Abstract: A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: October 15, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chien-Kang Chou, Ke-Hung Chen
  • Patent number: 8552559
    Abstract: A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: October 8, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
  • Patent number: 8546947
    Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 1, 2013
    Assignee: Megica Corporation
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
  • Publication number: 20130242500
    Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
    Type: Application
    Filed: May 1, 2013
    Publication date: September 19, 2013
    Applicant: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu
  • Patent number: 8535976
    Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: September 17, 2013
    Assignee: Megica Corporation
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
  • Patent number: 8531038
    Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: September 10, 2013
    Assignee: Megica Corporation
    Inventor: Mou-Shiung Lin
  • Publication number: 20130221512
    Abstract: A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.
    Type: Application
    Filed: March 29, 2013
    Publication date: August 29, 2013
    Applicant: Megica Corporation
    Inventor: Megica Corporation
  • Patent number: 8519552
    Abstract: A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: August 27, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Chiu-Ming Chou
  • Publication number: 20130214387
    Abstract: The present disclosure provides a method for forming a chip structure with a resistor. A semiconductor substrate is provided and has a surface. A plurality of electronic devices and a resistor is formed on the surface of the semiconductor substrate. A plurality of dielectric layers and a plurality of circuit layers are formed over the semiconductor substrate. The dielectric layers are stacked over the semiconductor substrate and have a plurality of via holes. Each of the circuit layers is disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. A passivation layer is formed over the dielectric layers and the circuit layers. A circuit line is formed over the passivation layer, wherein the circuit line passes through the passivation layer and is electrically connected to the resistor.
    Type: Application
    Filed: March 26, 2013
    Publication date: August 22, 2013
    Applicant: Megica Corporation
    Inventor: Megica Corporation
  • Patent number: 8503186
    Abstract: System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: August 6, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20130193553
    Abstract: A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.
    Type: Application
    Filed: January 30, 2007
    Publication date: August 1, 2013
    Applicant: MEGICA CORPORATION
    Inventor: Mou-Shiung Lin
  • Patent number: 8492870
    Abstract: A chip package comprising a glass substrate, wherein a first opening in the glass substrate passes vertically through the glass substrate, a semiconductor chip, a wiring structure comprising a first portion in the first opening and a second portion over the glass substrate, wherein the first portion is connected to the semiconductor chip, wherein the wiring structure comprises a passive device, wherein the wiring structure comprises copper, and a dielectric layer over the glass substrate and on the wiring structure, wherein a second opening in the dielectric layer is over a contact point of the wiring structure, and the contact point is at a bottom of the second opening.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: July 23, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
  • Patent number: 8492900
    Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: July 23, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 8487400
    Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: July 16, 2013
    Assignee: Megica Corporation
    Inventor: Mou-Shiung Lin
  • Patent number: 8482127
    Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: July 9, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 8481418
    Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 9, 2013
    Assignee: Megica Corporation
    Inventors: Jin-Yuan Lee, Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
  • Patent number: 8471361
    Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 25, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang