Abstract: A bonding process includes the following process. A bump is formed on a first electric device. A patterned insulation layer is formed on a second electric device, wherein the patterned insulation layer has a thickness between 5 ?m and 400 ?m, and an opening is in the patterned insulation layer and exposes the second electric device. The bump is joined to the second electric device exposed by the opening in the patterned insulation layer.

Abstract: A device is described which includes a waveguide structure for signal transmission and power/ground delivery The waveguide structure includes a signal transmission part for transmitting an optical signal from an illuminant device to a detector. The signal transmission part may include transparent polymer, diamond or glass. The signal transmission part is used for a waveguide. The waveguide structure further includes a power/ground delivery part surrounding the signal transmission part. The power/ground delivery part is composed of at least one metal layer. Thus, the waveguide structure can provide an optical-signal transmission with high speed and high volume through the signal transmission part, while a stable power or ground reference can be provided to multiple units through the power/ground delivery part.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A semiconductor chip or wafer includes a passivation layer, a pad and a bump. The pad is exposed by an opening in the passivation layer. The bump is connected to the pad, wherein the area of the connection between the pad and the bump is larger than 30,000 ?m2.

Abstract: An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip.

Abstract: A chip assembly includes a semiconductor chip, a bump and an external circuit. The semiconductor chip includes a semiconductor substrate, a transistor in and on the semiconductor substrate, multiple dielectric layers over the semiconductor substrate, a metallization structure over the semiconductor substrate, wherein the metallization structure is connected to the transistor, and a passivation layer over the metallization structure, over the dielectric layers and over the transistor. The bump is connected to the metallization structure through an opening in the passivation layer, wherein the bump includes an adhesion/barrier layer and a gold layer over the adhesion/barrier layer. The external circuit can be connected to the bump using a tape carrier package (TCP), a chip-on-film (COF) package or a chip-on-glass (COG) assembly.

Abstract: In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.

Abstract: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Abstract: A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

Abstract: System-in packages, or multichip modules, are described which can include multi-layer chips in a multi-layer polymer structure, on-chip metal bumps on the multi-layer chips, intra-chip metal bumps in the multi-layer polymer structure, and patterned metal layers in the multi-layer polymer structure. The multi-layer chips in the multi-layer polymer structure can be connected to each other or to an external circuit through the on-chip metal bumps, the intra-chip metal bumps and the patterned metal layers. The system-in packages can be connected to external circuits through solder bumps, meal bumps or wirebonded wires.

Abstract: A semiconductor chip includes first, second and third metal interconnects and an insulating layer over a semiconductor substrate. First, second and third openings in the insulating layer are over first, second and third contact points of the first, second and third metal interconnects, respectively. A fourth metal interconnect over the insulating layer connects the first and second contact points. The fourth metal interconnect includes a first metal layer and a second metal layer. The first metal layer is under but not at a sidewall of the second metal layer. The semiconductor chip includes a metal bump connected to the third contact point through the third opening, and a dielectric layer over the fourth metal interconnect and the insulating layer. No opening is in the dielectric layer on the fourth metal interconnect, and the metal bump has a top higher than a top surface of the dielectric layer.

Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Abstract: Chip assemblies are disclosed that include a semiconductor substrate, multiple devices in and on the semiconductor substrate, a first metallization structure over the semiconductor substrate, and a passivation layer over the first metallization structure. First and second openings in the passivation layer expose first and second contact pads of the first metallization structure. A first metal post is positioned over the passivation layer and over the first contact pad. A second metal post is positioned over the passivation layer and over the second contact pad. A polymer layer is positioned over the passivation layer and encloses the first and second metal posts. A second metallization structure is positioned on the polymer layer, on the top surface of the first metal post and on the top surface of second metal post. The second metallization structure includes an electroplated metal. Related fabrication methods are also described.

Abstract: The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.

Abstract: A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Abstract: A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.