Abstract: A spiral probe includes a tapered distal end portion (2) configured to be brought into direct contact with an inspection object, a hollow, nearly cylindrical distal body (3) extending in one direction from the base of the distal end portion (2), a hollow, nearly cylindrical flexible portion (4) integral with and continuously extending in the one direction from the distal body (3) and having a spiral outer peripheral surface, and a hollow, nearly cylindrical proximal end portion (5) integral with and continuously extending in the one direction from the flexible portion (4), wherein the distal body (3), the flexible portion (4) and the proximal end portion (5) have outer peripheral surfaces aligned with each other in the one direction.

Abstract: A thin conductive layer which is to form a conductor pattern (18) is prepared, a mask layer (3) is formed on the conductive layer except a plurality of actual connection spots and at least one dummy connection spot on the conductive layer, actual solder pads (6) and a dummy solder pad (7) are formed, with use of solder, on the actual connection spots and the dummy connection spot, respectively, where the conductive layer is exposed, connection terminals (9) of an electric or electronic component (8) are connected to the actual solder pads (6), an insulating base (16) of resin is formed which is laminated directly on or indirectly via the mask layer (3) on the conductive layer and in which the component (8) is embedded, and part of the conductive layer is removed by using the dummy solder pad (7) as a reference, to form the conductor pattern (18).

Abstract: The purpose of the present invention is to provide a wiring substrate from which a metal film cannot be detached easily. A process for forming a metal film comprises a step (X) of applying an agent containing a compound (?) onto the surface of a base and a step (Y) of forming a metal film on the surface of the compound (?) by a wet-mode plating technique, wherein the compound (?) is a compound having either an OH group or an OH-generating group, an azide group and a triazine ring per molecule, and the base comprises a polymer.

Abstract: A component-embedded substrate includes an electrically insulating base (11) of resin, an electric or electronic embedded component (8) and a dummy embedded component (7) both embedded in the insulating base (11), a conductor pattern (18) formed on at least one side of the insulating base (11) and connected directly to or indirectly via a connection layer (6) to the embedded component (8) and the dummy embedded component (7), and a mark (10) formed on a surface of the dummy embedded component (7) and used as a reference when the conductor pattern (18) is formed, whereby positional accuracy of the conductor pattern (18) relative to the embedded component (8) can be improved.

Abstract: A printed wiring board has a first wiring layer formed at least on one surface of an insulative substrate, an insulating layer formed as covering the first wiring layer, and a second wiring layer formed on the insulating layer. The insulating layer is formed of a cured insulative sheet made of a high-stiff sheet-type reinforcing material containing resin. The first and second wiring layers are electrically connected to each other through at least one hole having a bottom. The second wiring layer is united with the insulating layer at an interface thereof with a conductive material of the second wiring layer injected into concave sections provided on the interface. Another printed wiring board has an insulative substrate having a first surface and a second surface, a first insulating layer and a second insulating layer formed on the first surface and the second surface, respectively, and a first wiring layer formed on the first insulating layer and a second wiring layer formed on the second insulating layer.

Abstract: A circuit board including a capacitor structure formed on a surface of an insulating substrate, wherein the capacitor structure includes paired linear conductive layers arranged on the surface of the insulating substrate, parallel to each other with a predetermined distance between them, and a dielectric material filled in a groove defined by those surfaces of the paired linear conductive layers which face each other and the surface of the insulating substrate.

Abstract: A circuit board including a capacitor structure formed on a surface of an insulating substrate, wherein the capacitor structure includes paired linear conductive layers arranged on the surface of the insulating substrate, parallel to each other with a predetermined distance between them, and a dielectric material filled in a groove defined by those surfaces of the paired linear conductive layers which face each other and the surface of the insulating substrate.

Abstract: A core substrate (B) for being used in producing a multilayer circuit board in a manner that a plurality of unit circuit boards are laid on the upper and lower surfaces of the core substrate comprises two insulation layers (10A, 10B) laid with a conductor land part (11A) between. The insulation layers have a pair of laser-machined holes (12A, 12B) above and below the conductor land part, each extending from the surface of the insulation layer up to the conductor land part. The pair of laser-machined holes are filled with an electroplating material to form a pair of columnar conductors (13A, 13B) electrically connected through the conductor land part. Since all layers can be interconnected through a series structure formed of an electro copper plating material, the core substrate is useful for producing a multilayer circuit board in which low resistance and fine patterning can be realized.

Abstract: A circuit board which is formed with bump patterns subject to a narrow variation in height on the surface of the circuit board, and which permits high-density packaging of a semiconductor component thereon. In this circuit board, conductor circuits formed by electroplating are embedded in an insulating base that is formed of a resist layer and an insulating substrate, and bumps are exposed in the surface of the insulating base. The bumps and the conductor circuits are connected electrically with one another by means of pillar-shaped conductors that are formed by electroplating. Each bump is a multilayer structure in two or more layers formed by successively depositing different electrically conductive materials by electroplating.

Abstract: A circuit board which is formed with bump patterns subject to a narrow variation in height on the surface of the circuit board, and which permits high-density packaging of a semiconductor component thereon. In this circuit board, conductor circuits formed by electroplating are embedded in an insulating base that is formed of a resist layer and an insulating substrate, and bumps are exposed in the surface of the insulating base. The bumps and the conductor circuits are connected electrically with one another by means of pillar-shaped conductors that are formed by electroplating. Each bump is a multilayer structure in two or more layers formed by successively depositing different electrically conductive materials by electroplating.

Abstract: A circuit board, which is formed with bump patterns subject to a narrow variation in height on the surface of the circuit board, and which permits high-density packaging of a semiconductor component thereon. In this circuit board, conductor circuits formed by electroplating are embedded in an insulating base that is formed of a resist layer and an insulating substrate, and bumps are exposed in the surface of the insulating base. The bumps and the conductor circuits are connected electrically with one another by means of pillar-shaped conductors that are formed by electroplating. Each bump is a multilayer structure in two or more layers formed by successively depositing different electrically conductive materials by electroplating.

Abstract: A process for producing a copper-clad laminate is disclosed which includes the steps of (a) contacting the surface of a conductive carrier with a catalyst liquid containing at least one noble metal selected from the group consisting of Pd, Pt, Ru, Au, and Ag; (b) subsequently forming a copper foil layer on the treated surface of the conductive carrier by copper electroplating; (c) laminating an insulating base on the copper foil layer by hot-press bonding; and (d) separating the conductive carrier from the resulting laminate. The copper foil layer in the resulting copper-clad laminate has reduced pinholes and exhibits isotropic mechanical characteristics.

Abstract: A process for producing a copper-clad laminate, which comprises a step (S2) of forming a copper foil of at least several micrometers on a planar conductive substrate by electrolysis, a step (S3) of roughening the surface of the copper foil, a step (S4) of laminating the copper foil together with the conductive substrate on an insulating substrate and tightly integrating the assembly by applying pressure and heat, and a step (S5) of separating only the conductive substrate. A metal film may exist between the conductive substrate and the copper foil. When the metal film has a thickness of 0.1 to 3 .mu.m, only the conductive substrate is separated with the metal film being firmly adhered to the copper foil surface and, when the metal film has a thickness of 70 to 250 .mu.m, it is separated together with the conductive substrate after the lamination. The copper foil formed by high-speed plating under the conditions of 6 to 12.0 m/sec in solution contact speed and 0.8 to 4.0 A/cm.sup.

Abstract: A method suited for producing a conductor circuit board having a high-density, fine circuit pattern. Conductor circuits and dummy circuits are formed on the surface of a planar, electrically conductive substrate, and after removing a resist mask, unnecessary dummy circuits are removed. A thin metal film is formed over the surface of the conductive substrate and the surfaces of the conductor circuits and remaining dummy circuits. An insulating substrate is superposed on the surface of the conductive substrate on which the thin metal film is formed, and the two substrates are pressure-bonded together with heat applied thereto. Subsequently, only the conductive substrate is removed, and exposed portions of the thin metal film are removed by etching.

Abstract: The present invention relates to a connector for optical fiber used as optical communication parts, in particular to a ferrule which is one member of a plug side of the connector, a pointed end portion of the ferrule being partially cut off, and the optical fiber being inserted and fixed into the ferrule, the terminal treatment of the optical fiber is practiced by injuring the circumferential surface of the pointed end portion of the optical fiber and by cleaving the pointed end portion of the optical fiber.

Abstract: A thin metal layer with a thickness of 1 to 5 .mu. is formed electrolytically (S2) on an electrically conductive single-plate substrate having a predetermined roughness, a resist mask is formed (S3) on the surface of the thin metal layer, and a conductor circuit is then electroformed thereon (S4) using copper. After the surface of the conductor circuit is roughened (S5), the conductor circuit, along with the single plate and the interposed thin metal layer, is stacked on an insulating substrate for lamination, and the individual layers are adhered integrally to one another by the application of heat and pressure (S7). Then, the single plate only is peeled off (S8), and the exposed thin metal layer is removed by etching (S9). The thin metal layer and the conductor circuit are electroplated under high-speed conditions including a solution contact speed of 2.6 to 20 m/sec and a current density of 0.15 to 4.0 A/cm.sup.