Abstract: A system and method for performing routing in a computer network implementing in-network computing, including: obtaining information regarding compute resources allocated to an in-network compute operation; and allocating a path and bandwidth for ordinary network traffic based on the allocated compute resources.

Abstract: A peripheral device includes a bus interface, a first processor and a second processor. The bus interface is to communicate over a peripheral bus. The first processor is to manage communication over the peripheral bus by executing bus-maintenance software code, the bus-maintenance software code being executed from one or more first layers of a multi-layer memory. The second processor is to update the bus-maintenance software code from an existing version to an updated version, by (i) loading the updated version to one or more second layers of the multi-layer memory, higher in hierarchy than the one or more first layers, and (ii) invalidating the existing version in the one or more first layers, thereby forcing fetching of the updated version from the one or more second layers to the one or more first layers and to start executing the updated version.

Abstract: Systems, computer program products, and methods are described herein for intelligent data compression, in accordance with an embodiment of the invention. The present invention may be configured to receive a plurality of files for storage in a database and perform a series of steps iteratively, for each file of the plurality of files, and until each file of the plurality of files is represented in the database. The series of steps may include identifying one or more data points in the respective file, where each identified data point was previously unidentified in the database and adding the identified one or more data points to the database. The series of steps may also include identifying one or more features of the respective file for storage in the database and storing the identified one or more features in the database as a surrogate for the respective file.

Abstract: A receiver device includes circuitry to measure an error vector of a pulse amplitude modulation (PAM) sequence in a signal received from a transmitter and control logic coupled to the circuitry. The control logic removes estimated linear components from the measured error vector to generate a non-linear error vector. The control logic further determines, with reference to a set of lookup table (LUT) values, one or more tuning parameters for the PAM sequence based on the non-linear error vector and modifies the set of LUT values according to the one or more tuning parameters. The control logic further provides the modified set of LUT values to the transmitter, which when used by the transmitter to add digital pre-distortion to the PAM sequence, causes the non-linear error to be at least partially removed from the signal.

Abstract: A method and system are provided for limiting unnecessary data traffic on the data communication connections connecting various system components, including the various levels of system memory. Some embodiments may include processing a buffer allotment request and/or a buffer release command in coordination with a system or network operation requiring temporary storage of data in a memory buffer. The buffer allotment request may be capable of indicating the amount of storage space required on the memory buffer to execute the system or network operation. The system may be capable of precluding the system or network operation from executing until there is sufficient space in the memory buffer to complete the operation without evicting operational data from the memory buffer. In some embodiments, the buffer release command may signal completion of the system or network operation and release of the utilized memory buffer space for other operations.

Abstract: In one embodiment, a device, includes a network interface to receive a SYN packet from a client via a packet data network to establish a connection with a server, and a processor to run an express data path (XDP) to accelerate at least a part of a SYN cookie connection process.

Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.

Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.

Abstract: A wafer includes a semiconductor substrate, multiple photonics devices and a test coupler. The multiple photonics devices are fabricated on the substrate and have multiple respective ports. The test coupler is disposed on the wafer and is configured to couple an optical test signal between a tester and the multiple ports of the multiple photonics devices during testing of the photonics devices.

Abstract: A method includes providing a plurality of processes interconnected by a network, each of the plurality of processes being configured to hold a block of data destined for others of the plurality of processes. A set of data for all-to-all data exchange is received from one or more of the processes. The set of data is configured as a plurality of blocks of data in a matrix as matrix data, the matrix being distributed among the plurality of processes. The matrix data is transposed by changing the position of selected blocks of data of the plurality of blocks of data relative to the other blocks of data of the plurality of the blocks of data, without changing the structure of each of the blocks of data. The transposed matrix data is over the network and is then received, repacked, and conveyed to destination processes.

Abstract: A transceiver module for providing operational resilience is presented. The transceiver module is configured to receive first data via a first optical module in a first configuration of operation and detect, using an adapter that is operationally connected to the first optical module, an operational failure of the first optical module. In response to detecting the operational failure, the transceiver module is configured to switch, via the adapter, from the first configuration of operation to a second configuration of operation by: automatically engaging a second optical module; triggering the first data that was initially directed into a first input port of the first optical module to be directed into a second input port of the second optical module; and receiving the first data from a second output port of the second optical module.

Abstract: A device may include a printed circuit board (PCB), a plurality of surface-mount devices disposed on the PCB, wherein a thermal mass of each of the surface-mount devices ranges between a first thermal mass value and a second thermal mass value that is greater than the first thermal mass value, and a plurality of thermal capacitors disposed on the PCB, wherein a thermal mass of each of the thermal capacitors is equal to or greater than the first thermal mass value of the surface-mount devices.

Abstract: A network device comprises processing circuitry configured to: receive a plurality of data chunks from at least one source; form a composite data chunk from at least first and second data chunks of the plurality of data chunks; process the composite data chunk to identify a match between a first pattern of characters within the composite data chunk and a stored pattern of characters; and validate or invalidate the match based on metadata of the composite data chunk.

Abstract: Apparatuses, systems, and techniques for classifying one or more computer programs executed by a host device as being ransomware using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service to protect one or more computer programs executed by the host device. The security service obtains a series of snapshots of data stored in the physical memory and extracts a set of features from each snapshot of the series of snapshots, each snapshot representing the data at a point in time. The security service classifies a process of the one or more computer programs as ransomware or non-ransomware using the set of features and outputs an indication of ransomware responsive to the process being classified as ransomware.

Abstract: A substrate carrier and a mechanism for moving the substrate carrier through a chemical vapor deposition system are provided. The substrate carrier includes a cylindrical housing having an interior surface. A plurality of plurality of shelves fixed to the interior surface, each shelf configured to support at least one substrate. The substrate carrier may include a connector configured to engage the substrate carrier with the mechanism. The mechanism may include a moveable arm and a motor configured to actuate the moveable arm. The moveable arm may include an actuating member connected to the motor and configured to move the moveable arm between a retracted state and an extended state. The moveable arm may be configured to operate in a chamber having a first pressure and a first temperature and the motor may be configured to operate in an environment having a second pressure.

Abstract: An example method for dynamic packet routing using prioritized groups includes: receiving, by a processing device, routing information specifying a plurality of paths to a network destination, wherein each path is associated with a respective cost metric value; associating a first subset of the plurality of paths with a first priority routing group for the network destination, wherein each path of the first subset satisfies a first cost criterion based on a cost metric value of the path; associating a second subset of the plurality of paths with a second priority routing group for the network destination, wherein each path of the second subset satisfies a second cost criterion; and storing, in a forwarding information data structure, a first definition of the first priority routing group and a second definition of a second priority routing group.

Abstract: A high performance mechanism for exporting peripheral services and offloads using Direct Memory Access (DMA) engine is presented. The DMA engine comprises a ring buffer, a DMA memory, and a DMA engine interface operatively coupled to the ring buffer and the DMA memory. The DMA engine interface is configured to retrieve, from the ring buffer, a first DMA request; extract first transfer instructions from the first DMA request; retrieve a first data corresponding to the first DMA request from the DMA memory; and execute the first DMA request using the first data based on at least the first transfer instructions.

Abstract: An electronic sub-assembly, which may include: a ceramic substrate having a top surface and a bottom surface, a plurality of layers of ceramic material disposed between the top surface and the bottom surface of the substrate, and a plurality of conductive structures passing through the substrate between the top surface and the bottom surface of the substrate; and a ball grid array disposed on the bottom surface of the substrate, the ball grid array comprising a plurality of solder balls, wherein at least a portion of the solder balls are connected to at least a portion of the conductive structures.

Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.