Abstract: A processing device in a memory system identifies a workload condition associated with a memory device. The processing device determines a host rate associated with the memory device based on the workload condition. The processing device detects a change in a condition of the memory device from a first state condition to a second state condition. The processing device determines, while the memory device is in the second state condition, an adjusted host rate, wherein the adjusted host rate is used to determine a credit consuming rate for a host operation.

Abstract: A method includes: receiving, from a vehicle approaching a trust zone, an identifier corresponding to an identity of the vehicle; verifying, by a computing device (e.g., an access server at a gate of the trust zone) and using the identifier, the identity of the vehicle; and comparing the identity of the vehicle with a set of authorized identities stored in a database.

Abstract: A semiconductor device includes a memory partition. The semiconductor device further includes a plurality of registers. A first register of the plurality of registers, when in operation, controls an operation associated with the memory partition. The semiconductor device additionally includes a memory controller. When in operation, the memory controller accesses a first location of the memory partition concurrently with accessing the first register.

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

Abstract: Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

Abstract: A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic is to perform operations including: causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first erase distribution programmed below an erase threshold voltage (Vt) level and a first voltage distribution programmed relative to a first Vt level; and causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second erase distribution programmed relative to the first Vt level and a second voltage distribution programmed relative to a second Vt level.

Abstract: Bit line noise suppression and related apparatuses, methods, and computing systems are disclosed. An apparatus includes a complementary metal-oxide-semiconductor (CMOS) wafer and a memory cell wafer. The CMOS wafer includes CMOS wafer contact pads and sense amplifier circuitry electrically connected to some of the CMOS wafer contact pads. The memory cell wafer includes memory cell wafer contact pads and bit lines electrically connected to some of the memory cell wafer contact pads. The bit lines include primary bit lines and secondary bit lines. Each of the secondary bit lines extends in parallel proximate to a corresponding one of the primary bit lines. A cross intersection of a first primary bit line with a first secondary bit line located proximate to a parity intersection of a second primary bit line with a second secondary bit line. The first primary bit line is adjacent to the second primary bit line.

Abstract: A semiconductor device assembly is provided. The assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of semiconductor dies having a second set of planform dimensions different from the first set disposed over a second location on the substrate, and an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. The first stack of semiconductor dies has a first planform area, the second stack of semiconductor dies has a second planform area, and a sum of the first and second planform areas can be at least 50%, 67%, 75% or even more of an area of the package substrate.

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.

Abstract: Some memory dice in a stack can be connected externally to the stack and other memory dice in the stack can be connected internally to the stack. The memory dice that are connected externally can act as interface dice for other memory dice that are connected internally thereto. Data protection and recovery schemes provided for the stacks of memory dice can be based on data that are transferred in a single data stream without a discontinuity between those data transfers from the memory dice of the stacks.

Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.

Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

Abstract: Systems, apparatuses, and methods related to access request management using sub-commands. Access requests received from a host system can be managed using a respective set of sub-commands corresponding to each access request and whose status can be tracked. Tracking how far access requests are processed at a fine granularity (of sub-commands) can provide efficient management of the access requests that can reduce a gap latency in processing multiple access requests.

Abstract: Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.

Abstract: The disclosed embodiments are directed to detecting persons or animals trapped in vehicles and providing automated assistance to such persons or animals. In one embodiment a method is disclosed comprising detecting that a vehicle is stopped; activating at least one camera and recording at least one image of an interior of the vehicle using the at least one camera; classifying the at least one image using a machine learning model; and operating at least one subsystem of the vehicle in response to detecting that classifying indicates that a person or animal is present in the at least one image.

Abstract: Disclosed are devices and methods for improving the pre-booting of electronic control unit devices in vehicles. In one embodiment, a method is disclosed comprising detecting a triggering of a pre-booting condition based on one or more interactions with a vehicle; transmitting a power-on signal to at least one electronic control unit (ECU) in the vehicle, the at least one ECU operating in a low-power state; and fully booting the at least one ECU upon determining that the vehicle has been started.