Patents Assigned to Micronas Semiconductors, Inc.
  • Patent number: 7545888
    Abstract: A method of controlling a digital demodulator (922) coupled to an equalizer (930) includes the steps of generating an equalizer value (930A), filtering (944) the equalizer value (930A) to obtain a post filter output, subtracting the equalizer output signal (930C) from the decoded data (930D) and generating an error value (924A). The post filter output is correlated (948) with the error value (924A) to obtain a correlated value (74A). A control signal is developed from the correlated value and is used to adjust the digital demodulator (922).
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: June 9, 2009
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Jilian Zhu, Richard W. Citta, Scott M. Lopresto, Shidong Chen
  • Patent number: 7504890
    Abstract: A data-directed frequency-and-phase lock loop for an offset-QAM modulated signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is phase-shifted by a second multiplier, then convolved by a third multiplier. The output of the third multiplier is split, with each portion being passed through a frequency-shift multiplier and a frequency-and-phase lock loop. The output of the two frequency-and-phase lock loops is summed and returned to the VCO to complete the feedback loop.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: March 17, 2009
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Richard W. Citta, Scott M. LoPresto, Jingsong Xia, Wenjun Zhang
  • Patent number: 7418034
    Abstract: An adaptive equalizer comprises a trellis decoder; a mapper coupled to the output of the trellis decoder; and a decision feedback equalizer coupled to the output of the mapper. Each of the taps receives as input via the mapper output from a different one of the stages of the trellis decoder.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: August 26, 2008
    Assignee: Micronas Semiconductors. Inc.
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. LoPresto, Wenjun Zhang
  • Patent number: 7376181
    Abstract: A DFE comprises a trellis decoder and a plurality of sub-filter pipelines. Each of the plurality of sub-filter pipelines is fed intermediate decoded symbols of one of the stages in a trace-back chain of a current decoding bank. The DFE output is formed by summing the plurality of sub-filter pipelines.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: May 20, 2008
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Shidong Chen, Jilian Zhu, Xiaojun Yang
  • Publication number: 20080107168
    Abstract: A digital receiver for processing a signal received from a channel includes a digital demodulator and an equalizer coupled to the digital demodulator. The equalizer includes a feedforward filter and a decision feedback equalizer (DFE), wherein the feedforward filter includes a plurality of feedforward filter taps. Coefficients are associated with the plurality of feedforward filter taps and the values of all of the coefficients associated with the plurality of feedforward filter taps are dynamically determined.
    Type: Application
    Filed: April 8, 2005
    Publication date: May 8, 2008
    Applicant: MICRONAS SEMICONDUCTORS, INC.
    Inventors: Jingsong Xia, Shidong Chen, Richard W. Citta, Gopalan Krishnamurthy, Scott M. Lopresto, David A. Willming, Xiaojun Yang, Jilian Zhu
  • Patent number: 7321642
    Abstract: A digital equalizer for interpreting a digital signal including convolutionally encoded symbols and synchronization symbols outside the convolutional code comprises a combined trellis encoder and DFE. The synchronization symbols are re-inserted into the input of the DFE in order to restore time domain continuity created by removal of the synchronization symbols.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: January 22, 2008
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Shidong Chen, Jilian Zhu, Xiaojun Yang
  • Publication number: 20080008280
    Abstract: A method of controlling sampling frequency and sampling phase of a sampling device from a value generated by an equalizer coupled to the sampling device includes the steps of generating a complex representation of the value developed by the equalizer and generating a representation of a decision from an output of the equalizer. The complex representation and the decision representation are correlated to obtain a sampling error estimate. The sampling error estimate is used to adjust the sampling frequency and sampling phase of the sampling device.
    Type: Application
    Filed: April 8, 2005
    Publication date: January 10, 2008
    Applicant: MICRONAS SEMICONDUCTORS, INC.
    Inventors: Jilian Zhu, Richard Citta, Scott Lopresto, David Willming, Shidong Chen
  • Patent number: 7272203
    Abstract: A data-and-pilot directed frequency-and-phase lock loop for an offset-QAM modulated signal having a pilot signal comprising a pilot acquisition loop and a pair of data-directed acquisition loops. The pilot is extracted from the main signal by a pilot filter, then used both by the pilot acquisition loop and to remove the pilot from the signal to the data-directed acquisition loops. The outputs of the pilot and the two data-directed acquisition loops are summed and returned to the VCO to complete the feedback loop.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: September 18, 2007
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Richard W. Citta, Scott M. LoPresto, Jingsong Xia, Wenjun Zhang
  • Patent number: 7190744
    Abstract: An equalizer comprises: an FIR; a trellis decoder coupled to the FIR; a mapper coupled to the trellis decoder; and a decision feedback equalizer coupled to the mapper. The decision feedback equalizer receives the mapped and scaled output of the trellis decoder as input and an error signal is generated by subtracting an output of the decision feedback equalizer from the input to the trellis decoder.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: March 13, 2007
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. LoPresto, Wenjun Zhang
  • Patent number: 7130344
    Abstract: An adaptive equalizer comprises a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: October 31, 2006
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. LoPresto, Wenjun Zhang, Hangbin Song
  • Patent number: 7072392
    Abstract: A digital equalizer comprises a matched filter that, in conjunction with an FIR filter, assures a single peak with substantially greater energy than other peaks caused by ghosts, thereby permitting synchronization even with multiple, arbitrarily strong ghosts caused by strong multipathing, multiple transmitters, or both.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: July 4, 2006
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. LoPresto, Wenjun Zhang
  • Patent number: 6995617
    Abstract: A data-directed frequency-and-phase lock loop for an offset-QAM modulated signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is phase-shifted by a second multiplier, then convolved by a third multiplier. The output of the third multiplier is split, with each portion being passed through a frequency-shift multiplier and a frequency-and-phase lock loop. The output of the two frequency-and-phase lock loops is summed and returned to the VCO to complete the feedback loop.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: February 7, 2006
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Richard W. Citta, Scott M. LoPresto, Jingsong Xia, Wenjun Zhang
  • Patent number: 6980059
    Abstract: A data-directed frequency-acquisition loop capable of generating a frequency error having a magnitude and direction from a double sideband suppressed signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is convolved by a second multiplier. The I output of the second multiplier passes through a first low-pass filter. The filtered I output and the Q output are then multiplied by a third multiplier. The output of the third multiplier is filtered through a second low-pass filter, amplified, and return to the VCO to complete the feedback loop.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: December 27, 2005
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Richard W Citta, Scott M LoPresto, Jingsong Xia, Wenjun Zhang
  • Patent number: 6940557
    Abstract: An interlace-to-progressive scan conversion system comprises: a spatial line averaging prefilter; a motion estimator; a three-stage adaptive recursive filter. The motion estimator comprises: a 3-D recursive search sub-component having a bilinear interpolator; a motion correction sub-component having an error-function including penalties related to the difference between a given candidate vector and a plurality of neighboring vectors; a block erosion sub-component. The motion estimator assumes that motion is constant between fields. The three-stage adaptive recursive filter comprises: a first stage that selects between using static pixels data and moving pixels data from a next field; a second stage that selects a more valid set of data between motion compensated data from a previous field and the pixels selected by the first stage; a third stage that combines an intra-field interpolation with the more valid set of data selected by the second stage.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: September 6, 2005
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Benitius M. Handjojo, Wenhua Li
  • Patent number: 6829297
    Abstract: An adaptive equalizer comprises a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: December 7, 2004
    Assignee: Micronas Semiconductors, Inc.
    Inventors: Jingsong Xia, Richard W. Citta, Scott M. LoPresto, Wenjun Zhang, Hangbin Song