Abstract: Techniques for performing panoramic scaling are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion are disclosed that reduce the size and power requirements of video manipulation hardware by reducing the number of logic gates and memory buffers required when YC adjustment and color conversion are implemented as separate operations.

Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

Abstract: A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.

Abstract: A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.

Abstract: Techniques for performing combined scaling, filtering, and/or scan conversion are disclosed that reduce the amount of line buffer space required in the overall design of a video processing system. In particular, coefficients from all or a sub-set of the scaling, filtering (smoothing/sharpening), and scan conversion filters are combined into one representative coefficient that can be applied in a single generic algorithm. Thus, implementation costs are reduced, particularly in a system-on-chip implementations.

Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.

Abstract: A method, apparatus, computer medium, and other embodiments for selectably enabling a plurality of data transfer modes along one or more channels are described. In one embodiment, data transfer between a first device and a second device is controlled based on selecting a combination of access and operation modes. In another embodiment, a video processing system capable of selectably enabling a plurality of data transfer modes along one or more channels is described.

Abstract: A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.

Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

Abstract: Techniques for performing panoramic scaling are disclosed that reduce visible distortion in a panoramic image. Further, techniques for performing combined YC adjustment and color conversion are disclosed that reduce the size and power requirements of video manipulation hardware by reducing the number of logic gates and memory buffers required when YC adjustment and color conversion are implemented as separate operations.

Abstract: Techniques for performing combined scaling, filtering, and/or scan conversion are disclosed that reduce that amount of line buffer space required in the overall design of a video processing system. In particular, coefficients from all or a sub-set of the scaling, filtering (smoothing/sharpening), and scan conversion filters are combined into one representative coefficient that can be applied in a single generic algorithm. Thus, implementation costs are reduced, particularly in system-on-chip implementations.

Abstract: The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display.

Abstract: A demosaic system and method that supports multiple CFA pattern inputs is disclosed. The demosaic system is capable of handling both RGB Bayer input and CMYG input and perform demosaic operations on both inputs to recover full-color images from the raw input images. The system uses a variable number gradient demosiac process. The process uses a 5×5 neighborhood of sensor pixel data centered at the pixel under consideration. The process calculates a set of gradients corresponding to different directions within the neighborhood of the sensor pixel data. A threshold value is determined and a subset of gradients is selected from the set of gradients that fall below the threshold value. The system calculates estimation values for the missing color value and the actual measured center pixel color value obtained from the sensor data on directions that are within the subset of gradients below the threshold.

Abstract: A noise filter for a video processing system includes a block selector, a cost calculator, a cost table, a cost comparator, and a coefficient filter. The block selector is coupled to receive data from the quantization unit and selects blocks for additional filtering. The selected blocks are provided to the cost calculator determines a cost for each of the coefficients in the block using the cost table and the costs are summed. The cost comparator compares the total to a threshold, and filters the coefficients using the coefficient filter if the total is greater a preset threshold. The noise filter to the VLC unit then outputs the filter data.

Abstract: A system and method embed an audio signature in a video frame. An audio signature is generated from one bit a buffer input data. Two registers store an audio signature and reference count. According to an embodiment, the audio signature is generated left/right (L/R) interleaved with the left channel data in the most significant bit (MSB).

Abstract: A demosaic system and method that supports multiple CFA pattern inputs is disclosed. The demosaic system is capable of handling both RGB Bayer input and CMYG input and perform demosaic operations on both inputs to recover full-color images from the raw input images. The system uses a variable number gradient demosiac process. The process uses a 5×5 neighborhood of sensor pixel data centered at the pixel under consideration. The process calculates a set of gradients corresponding to different directions within the neighborhood of the sensor pixel data. A threshold value is determined and a subset of gradients is selected from the set of gradients that fall below the threshold value. The system calculates estimation values for the missing color value and the actual measured center pixel color value obtained from the sensor data on directions that are within the subset of gradients below the threshold.

Abstract: A demosaic system and method that supports multiple CFA pattern inputs is disclosed. The demosaic system is capable of handling both RGB Bayer input and CMYG input and perform demosaic operations on both inputs to recover full-color images from the raw input images. The system uses a variable number gradient demosiac process. The process uses a 5×5 neighborhood of sensor pixel data centered at the pixel under consideration. The process calculates a set of gradients corresponding to different directions within the neighborhood of the sensor pixel data. A threshold value is determined and a subset of gradients is selected from the set of gradients that fall below the threshold value. The system calculates estimation values for the missing color value and the actual measured center pixel color value obtained from the sensor data on directions that are within the subset of gradients below the threshold.

Abstract: A design technique is disclosed that allows video processing hardware designers to effectively employ the requirements of a video processing standard (e.g., H.264 specification or other such standard) during the hardware architecture design phase of the design process. The technique eliminates or otherwise reduces costly multiple passes through the resource intensive implementation and verification portions of the design process, and allows designers to make changes to the hardware architecture design, thereby ensuring verification at the implementation phase.

Abstract: This invention relates generally to hardware for scaling and filtering video data and more specifically to algorithms and techniques for accelerating scaling and filtering operations on digital video data. The hardware is designed so that scaling and filtering operations are combined and performed simultaneously where possible to speed manipulation of the video data. Efficient design of the system allows memory buffers and logic gates to be shared or eliminated to reduce the size, cost and power requirements of the hardware implementation.

Abstract: A method, apparatus, computer medium, and other embodiments for synchronizing control of one or more devices at predetermined times are described. A host scheduler loads a to-do list of predetermined events and corresponding time-tags into memory and broadcasts scheduled events to the devices to cause activation of the events on intended devices.