Patents Assigned to Mie Fujitsu Semiconductor Limited
  • Patent number: 9268885
    Abstract: A method can include selecting integrated circuit (IC) device fabrication process source variations; generating relationships between each process source variance and a device metric variance; and calculating at least one IC device metric value from the process source variations and corresponding relationships between each process source variance and a device metric variance.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 23, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventor: Jing Wang
  • Patent number: 9263523
    Abstract: An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: February 16, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Paul E. Gregory, Sachin R. Sonkusale, Weimin Zhang, Scott E. Thompson
  • Patent number: 9236466
    Abstract: A circuit can include at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the first conductivity type formed below the channel region.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: January 12, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Sang-Soo Lee, Heetae Ahn, Augustine Kuo
  • Patent number: 9231541
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: January 5, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawerence T. Clark, Scott E. Thompson
  • Patent number: 9224733
    Abstract: A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: December 29, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Pushkar Ranade, Sachin R. Sonkusale
  • Patent number: 9196727
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: November 24, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Patent number: 9184750
    Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: November 10, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Lawrence T. Clark
  • Patent number: 9154123
    Abstract: An integrated circuit can include a plurality of drive monitoring sections, each including at least one transistor under test (TUT) having a source coupled to a first power supply node, a gate coupled to receive a start indication, and a drain coupled to a monitor node, at least one monitor capacitor coupled to the monitor node, and a timing circuit configured to generate a monitor value corresponding to a rate at which the TUT can transfer current between the monitor node and the first power supply node; and a body bias circuit configured to apply a body bias voltage to at least one body region in which at least one transistor is formed; wherein the body bias voltage is generated in response to at least a plurality of the monitor values.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: October 6, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, Michael S. McGregor, Robert Rogenmoser, David A. Kidd, Augustine Kuo
  • Patent number: 9117746
    Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: August 25, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Samuel Leshner
  • Patent number: 9112057
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a semiconducting surface and forming a first epitaxial layer on the semiconducting surface. The first epitaxial layer includes a first semiconducting material doped in-situ with at least one dopant of a first conductivity type. The method also includes adding at least one dopant of a second conductivity type into one portion of the substrate to define at least one counter-doped region with an overall doping of the second conductivity type and at least one other region with an overall doping of the first conductivity type in the other portions of substrate. The method further includes forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer being a second semiconducting material that is substantially undoped.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: August 18, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Sameer Pradhan, Dalong Zhao, Lingquan Wang, Pushkar Ranade, Lance Scudder
  • Patent number: 9112484
    Abstract: An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 18, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, David A. Kidd, Chao-Wu Chen
  • Patent number: 9111785
    Abstract: A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: August 18, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Paul E. Gregory, Pushkar Ranade, Lucian Shifren
  • Patent number: 9112495
    Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 18, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, David A. Kidd, Augustine Kuo
  • Patent number: 9105711
    Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 11, 2015
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Lingquan Wang, Teymur Bakhishev, Dalong Zhao, Pushkar Ranade, Sameer Pradhan, Thomas Hoffmann, Lucian Shifren, Lance Scudder
  • Patent number: 9093550
    Abstract: Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 28, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Dalong Zhao, Pushkar Ranade, Bruce McWilliams
  • Patent number: 9093997
    Abstract: An integrated circuit can include at least one slew generator circuit comprising at least one body biasable reference transistor, the slew generator circuit configured to generate at least a first signal having a slew rate that varies according to characteristics of the reference transistor; a pulse generator circuit configured to generate a pulse signal having a first pulse with a duration corresponding to the slew rate of the first signal; and a counter configured to generate a count value corresponding to a duration of the first pulse.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: July 28, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: David A. Kidd, Edward J. Boling, Vineet Agrawal, Samuel Leshner, Augustine Kuo, Sang-Soo Lee, Chao-Wu Chen
  • Patent number: 9093469
    Abstract: An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped channel.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: July 28, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lucian Shifren, Scott E. Thompson, Paul E. Gregory
  • Patent number: 9070477
    Abstract: A method can include applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt); applying an array power supply voltage to cells of the SRAM that is near or below Vt; and in a write operation, reading data from at least a first group of the cells that is interleaved with a second group of the cells, and applying the read data to the bit lines of the first group of cells, while write data is applied to the bit lines of the second group of cells.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: June 30, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventor: Lawrence T. Clark
  • Patent number: 9054219
    Abstract: A method of fabricating semiconductor devices includes providing a semiconducting substrate. The method also includes defining a heavily doped region at a surface of the semiconducting substrate in at least one area of the semiconducting substrate, where the heavily doped region includes a heavily doped layer having a doping concentration greater than a doping concentration of the semiconducting substrate. The method also includes forming an additional layer of semiconductor material on the semiconducting substrate, the additional layer comprising a substantially undoped layer. The method further includes applying a first removal process to the semiconducting substrate to define an unetched portion and an etched portion, where the unetched portion defines a fin structure, and the etched portion extends through the additional layer, and then isolating the fin structure from other structures.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: June 9, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Scott E. Thompson
  • Patent number: 9041126
    Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 26, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim