Abstract: A plasma generator includes a cap (20) having a sintered porous aluminium cuttings diffusor disc (28) spaced from the underside of a horizontal apertured top of the cap to prevent arcing therebetween and formation of a plasma plume affecting the wafer being etched. A plasma zone of reactive gases is formed between the cap and the wafer by rf energy. Process gases are conducted through cap top apertures (26) to the zone and the resultant plasma etches the semiconductor wafer spaced in parallelism from the cap top. Arcing between the metal diffusor and the metal cap is prevented by a ledge (27) on the cap interior periphery forming a gap between the bottom surface of the cap top and top surface of the diffusor. Etching or sputtering of the cap is also prevented by increasing the surface area of the apertures in the cap top to prevent ions from gaining a level of kinetic energy greater than the sputter threshold energy.

Abstract: A unique programming circuit, suitable for use with programmable read-only memories (PROM), or other circuits utilizing programmable fuses, is provided which overcomes several distinct disadvantages of prior art programming circuits. The programming circuit of this invention includes a Darlington pair of programming transistors which allows only a single programming transistor to be made large in order to carry the large programming current, and only a single high current drive signal need be applied to the single programming transistor, thereby minimizing power consumption and integrated circuit die area.

Abstract: A CMOS semiconductor structure having insulation sidewall spacers whose width is selected independently for NMOS and PMOS devices. The width of the spacer is selected to reduce hot electron injection in the N channel device and to insure that the gate and source regions are aligned with or underlap the gate in the P channel device. A narrower spacer is used for the P channel device than for the N channel device which permits the formation of a P channel device having a threshold voltage less than 1 volt.

Abstract: A fall-through memory array comprising in a plurality of rows and columns a plurality of memory cells, each memory cell comprising a pair of cross-coupled transistors having three emitters, a collector and a base. Control potentials applied to a word line, coupled to each one of two of the emitters of each of the transistors, control the transfer of data bits from one row of such memory cells to another.

Abstract: A programmable array logic circuit is provided having a programmable AND gate array and having means for connecting individual AND gate outputs to the input of one or the other of a pair of neighboring OR gates. This allows the product terms to be shared between two outputs.

Abstract: A semiconductor die attach adhesive is provided which is formed of a plurality of spacers formed in a suspension of silver filled glass. In one embodiment of this invention, the spacers are spheres. The spacers utilized in one embodiment of this invention have a melting temperature below the temperature at which the solvents are evaporated from the die attach adhesive. In this manner, as the solvents are driven from the silver filled glass during the die attach operation, thus causing the volume of the silver filled glass to decrease, the spacers utilized in this invention partially melt, thus decreasing their thickness. This decreased thickness of the spacers decreases the separation between the die and the substrate, thus preventing the formation of voids within the die attach adhesive. In one embodiment, the spacers are formed of a lead/tin alloy.

Abstract: An integrated circuit package magazine and receptacle is provided in which one or both ends of a longitudinally elongated magazine tube (10) are cut-out to form inwardly facing spring gates (16) which have ends (18) abutting ends (22) of a series of integrated semiconductor packages (20) slidably contained on a rail surface (13) in the interior of the magazine. In its neutral inward position spring gate 16 functions to prevent egress of the semiconductor packages while allowing easy ingress of the packages by spring movement of the spring gate upwardly into a position in the same plane as the top wall (15) of the tube. The tube may take various exterior and interior configurations. Automatic release of semiconductor packages from the tube is provided by utilizing the tube in conjunction with a receptacle (30) having a longitudinal rail (34) onto which the magazine is insertable.

Abstract: An improved circuit for serial scan diagnosis is provided. A state register in the signal path of the digital system under diagnosis is coupled to a diagnostic shift register. Test data is introduced and removed through the diagnostic shift register through a serial input terminal and serial output terminal. For certain operations the serial input terminal becomes a control terminal whereby a minimum number of control lines is required.

Abstract: Shallow, boron implanted regions are formed by ion implanting. Disclosed is a PNP transistor device (lateral type) having a P type emitter region preferably made with a boron implant.

Abstract: A bus organized 16.times.16 (or 8.times.8) high-speed digital bus-organized multiplier/divider for high-speed, low-power operation is implemented on a single semiconductor chip. Four working registers each of 16 (or 8) bits are used in the system. These registers are a multiplier register, a multiplicand and divisor register, a first accumulator register for storing the least significant half of a double length product after a multiplication of the remainder after a division operation, and a second accumulator register which stores the most significant half of the product after a multiplication or the quotient after a division operation. A decoder is connected to the multiplicand and multiplier registers to implement the Modified Booth Algorithm and to encode the 16 (or 8) multiplier digits. The system operates to shift the multiplier number through the multiplier register to a position where the Modified Booth Algorithm encoding takes place.

Abstract: This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders of the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions.

Abstract: This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders of the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions.

Abstract: This disclosure relates to a high speed combinatorial 8 by 8 digital multiplier suitable for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits. The encoder includes five subsections which generate a plurality of control signals. Each of the plurality of control signals is inputted into a separate one of five multiplexor circuits each of which also receives inputs representative of eight multiplicand bits in accordance with implementation of the Modified Booth Algorithm. Each of the five multiplexer circuits provides a plurality of outputs, each of the pluralities of outputs representing a separate partial product of the multiplier and multiplicand inputs. The partial products are inputted to an array of carry-save adders. The final stage of the adder network includes a carry-look-ahead adder which produces sixteen outputs which represent the product of the multiplier and the multiplicand.

Abstract: This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders or the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions.

Abstract: This disclosure is directed to a First In First Out memory which comprises a register, an input control section, a register control section, and an output control section. The imput control section allows data to be entered into the First In First Out memory while the register control section shifts the data through the memory queing up at the locations closest to the output. The output control allows data to be taken out of the FIFO at a different rate than data is entered into the memory by the input control section. The register control section monitors the succeeding location and the previous location in the register to determine when data may be shifted in the register.

Abstract: This disclosure relates to a programmable write-once, read-only semiconductor memory array which has an improved current source for each bit line and an improved current sink for each Word line. This programmable write-once, read-only semiconductor memory array utilizes a SCR (PNPN or NPNP) or the end of each Word line of the array to function as a current sink to minimize voltage drop on the Word line and a SCR (PNPN or NPNP) on each Bit line of the array for current sourcing purposes. This disclosure also relates to an integrated SCR (PNPN or NPNP) for use with a plurality of connected semiconductor devices to provide either a current sourcing or current sinking or drawing function for the plurality of connected semiconductor devices.

Abstract: Programmable array logic circuitry is disclosed wherein the outputs from a field programmable AND gate array are connected, non-programmably, to specified OR gates. For greater architectural and operational flexibility, registered outputs, internal feedback to the AND gate array, input/output pin interchangeability, and means for allowing performance of arithmetical, as well as logic, operations, are provided.