Abstract: The present invention relates to a monitor method for quality of metal Antireflection Coating (ARC) layer and, more particularly, to a fast and accurate monitor method for quality of metal ARC layer. By using of immersing a silicon wafer comprising an ARC layer into an acidic (such as a developer) or an alkalescent solution for about 200-300 seconds, according to the present invention, at weak points of the metal ARC layer there occur voids (defects) due to a Galvanic cell effect enhanced by these chemical solutions and then how many defects can be counted by a wafer defect inspector such as a KLA instrument so that quality of the metal ARC layer can be monitored by this defect number. Besides, Since the silicon wafer used as a sample for the wafer defect inspector simply comes from a production line, i.e. a developing process, rather than from other additional processing, said method allows for fast and accurately monitoring quality of the metal ARC layers.

Abstract: The present invention relates to a method for actually measuring misalignment of a via. According to the invention, a via is formed by etching an inter metal dielectric (IMD) layer using a photoresist with a via pattern as a mask so that via pattern can be accurately transferred to the inter metal dielectric layer. Then a patterned metal interconnection line underlying the inter metal dielectric layer is etched using the patterned inter metal dielectric layer as a mask and followed by a process of stripping the inter metal dielectric layer. After that, an actual misalignment can be detected by measuring relative distance between the patterned metal interconnection line and the via thereon through Scanning Electron Microscopy (SEM), by which overlay specifications for OSI instrument can be verified and adjusted.

Abstract: A method for checking the accuracy of a measuring instrument used for overlay registration includes the steps of forming a plurality of sets of overlay marks on a calibration mask, each of the overlay marks consisting of an outer box and an inner box, the central point of the outer box being shifted by a predetermined amount relative to the cental point of the inner box. A photoresist layer is then coated atop a control wafer and exposed through the calibration mask. Subsequently, the control wafer is developed to transfer the pattern of the mask to the photoresist layer atop the control wafer. The degree of accuracy of the measuring instrument used for overlay registration can be checked and measured by first taking a deviation of a measured shift amount for each set, which is defined as a difference between the measured shift amount and a corresponding predetermined value, and then taking a mean value of these deviations for all sets.

Abstract: The present invention relates to a method for prolonging life time of a dry etching chamber. A neck portion of the dry etching chamber, according to the present invention, is divided three sections, namely a first section, a second section and a third section in sequence from top of the neck portion to bottom thereof and each section has the same area. A first phase of a two-phase connection method, according to the present invention, then proceeds as the following. The first section is surrounded by an electrode coil connected to a rf power and the second section is surrounded by an electrode coil connected to the ground, not touching the electrode coil connected to the rf power, so that a plasma field within the dry etching chamber can be produced to perform a dry etching. The dry etching can be applied in production line until before life time of the first section comes to an end, i.e. about 95 % of life time of the dry etching chamber disclosed in prior art.

Abstract: The present invention relates to a method for increasing capacity of a capacitor. The method includes forming a polysilicon spacer on sidewall of a first polysilicon electrode and then treating the polysilicon spacer with a phosphoric acid to form a roughened surface area on the polysilicon spacer and the first polysilicon electrode. By this arrangement, the overall surface area of the polysilicon spacer and the first polysilicon electrode can be increased and the capacity of a capacitor can be increased accordingly.

Abstract: The present invention relates to a method of forming a barrier metal layer for a hot Al plug and its structure and more particularly to remarkably ameliorate the performance of a barrier metal layer preventing Al metal used as an interconnection layer from diffusing into a silicon substrate. A barrier metal layer according to the present invention is a stacked structure comprising a top layer of Tungsten (W) formed by a Chemical Vapor Deposition (CVD) method and a bottom layer of TiN. Then, a Al interconnection layer deposited at high temperature fills a plug and finishes a plug structure having advantages of low manufacturing cost and full prevention of Al diffusion.

Abstract: The present invention relates to a method of forming a self-aligned contact (SAC) window employing the liquid phase deposition (LPD) that allows low temperature deposition and selective growing of a LPD-SiO.sub.2 film as a stress-buffer layer to prevent WSi peeling during the formation of the SAC window. Specifically, the method comprises the steps of forming a nitride cap and a gate consisting of a WSi layer and a polysilicon layer over a surface of a silicon substrate followed by the formation of the sources and drain regions on the silicon substrate as well as by the process of forming the LPD-SiO.sub.2 film. A nitride spacer is formed at a sidewall of the nitride cap and the gate, and the SAC window is then formed by depositing a dielectric layer such as a SiO.sub.2 layer followed by exposing through a mask.

Abstract: A stacked capacitor of a DRAM cell has an increased storage electrode without increasing the total area and fabrication complexity of the DRAM cell. By disposing the storage electrode of a memory capacitor on an especially made rugged stacked oxide layer, the area of the storage electrode is enlarged and thus provides the higher capacitance. Then, by removing the rugged stacked oxide layer to expose the rugged surface of the storage electrode, the capacitance of a memory capacitor is additionally increased after covering the whole rugged surface of a of the storage electrode with a dielectric film.

Abstract: The present invention relates to a stacked capacitor of a DRAM cell, particully remarkably increasing a surface area of a storage electrode of a stacked capacitor without increasing an occupation area and a complexity of fabrication thereof. According to the invention, by use of depositing a protection polysilicon layer on a rugged polysilicon layer, which can provide an increased surface area of a storage electrode, a chemical oxide layer underlying the rugged polysilicon layer is protected by the protection polysilicon layer during a HF dip and thus a peeling of the rugged polysilicon layer as a result of the chemical oxide loss will not occur, thereby preventing a production yield loss.

Abstract: The present invention relates to a method of a sequencial WSi/.alpha.-Si sputtering process, more particularly to a method of in-situ wafer cooling for a sequencial WSi/.alpha.-Si sputtering process. A sputtering process of WSi and a sputtering process of .alpha.-Si are finished in a multi-chamber sputtering apparatus according to the invention; meanwhile, a wafer is cooled down by bolwing of inert gas before a process of sputtering .alpha.-Si starts. Thus, compared to traditional art of finishing WSi/.alpha.-Si sputtering in two apparatus, partial time of vacuuming and venting required in a sputtering process is saved according to the invention, thereby, shortening the production cycle time, reducing the possibility of wafer contamination, and suppressing the fabricating cost.

Abstract: A logical latch is permanently programmable to a selected state for use as a control circuit with extremely low power consumption in an integrated circuit.