Patents Assigned to Nanometrics Incorporated
  • Publication number: 20090229997
    Abstract: A sealing ring assembly and an improved method for mounting a sealing ring into an electrochemical cell used for Electrochemical Capacitance Voltage (ECV) profiling measurements. The ring is located in a holder having at least one secondary bore providing fluid communication between a forward face of the holder and the central bore of the ring, directed parallel to but tangentially offset relative to the inner wall of the central bore so as to impart a degree of rotational flow to electrolyte entering the sealing ring through the or each secondary bore which effectively removes gas bubbles and refreshes the electrolyte. The holder facilitates ring removal with a much reduced risk of damage to the delicate sealing surface.
    Type: Application
    Filed: May 21, 2009
    Publication date: September 17, 2009
    Applicant: Nanometrics Incorporated
    Inventors: Ian Christopher Mayes, James Gough, Ian Gilbert, Harvey Podgorney
  • Patent number: 7589834
    Abstract: A method of detecting surface particulate defects, and especially metal particulates, in semiconductors such as silicon, to characterise defects likely to have an effect on the electrical activity of such semiconductor materials, comprises exposing the surface of the semiconductor structure in the vicinity of a surface particulate to at least one high-intensity beam of light and collecting and processing the photoluminescence response; and using the result to identify unacceptable contamination levels resulting from diffusion of contaminant from particulate into semiconductor structure. Optionally, the semiconductor is annealed and photoluminescence responses collected before and after annealing to identify contaminant diffusion rates. Apparatus for the same is also described.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: September 15, 2009
    Assignee: Nanometrics Incorporated
    Inventor: Victor Higgs
  • Publication number: 20090190138
    Abstract: This disclosure provides methods for measuring asymmetry of features, such as lines of a diffraction grating. On implementation provides a method of measuring asymmetries in microelectronic devices by directing light at an array of microelectronic features of a microelectronic device. The light illuminates a portion of the array that encompasses the entire length and width of a plurality of the microelectronic features. Light scattered back from the array is detected. One or more characteristics of the back-scattered light may be examined by examining data from the complementary angles of reflection. This can be particularly useful for arrays of small periodic structures for which standard modeling techniques would be impractically complex or take inordinate time.
    Type: Application
    Filed: April 3, 2009
    Publication date: July 30, 2009
    Applicant: Nanometrics Incorporated
    Inventor: Christopher Raymond
  • Patent number: 7556725
    Abstract: A sealing ring assembly and an improved method for mounting a sealing ring into an electrochemical cell used for Electrochemical Capacitance Voltage (ECV) profiling measurements. The ring is located in a holder having at least one secondary bore providing fluid communication between a forward face of the holder and the central bore of the ring, directed parallel to but tangentially offset relative to the inner wall of the central bore so as to impart a degree of rotational flow to electrolyte entering the sealing ring through the or each secondary bore which effectively removes gas bubbles and refreshes the electrolyte. The holder facilitates ring removal with a much reduced risk of damage to the delicate sealing surface.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: July 7, 2009
    Assignee: Nanometrics Incorporated
    Inventors: Ian Christopher Mayes, James Gough, Ian Gilbert, Harvey Podgorney
  • Publication number: 20090148256
    Abstract: A chuck, which may hold a substrate during stress measurements, includes a number of pins that support the substrate. Each support pin has a dome shaped upper surface that contacts a bottom surface of a substrate when supporting the substrate. The dome shaped upper surface minimizes contact with the substrate as well as assists in maintaining the same contact location with the substrate regardless of substrate shape. The dome shaped upper surface may be formed of a layer of soft material having a high coefficient of static friction to hold the substrate stationary with respect to the pins when the chuck is accelerated moved during or between stress measurements. Additionally, the layer of soft material may be a thin layer that covers a hard internal dome to reduce creep.
    Type: Application
    Filed: December 10, 2007
    Publication date: June 11, 2009
    Applicant: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 7532317
    Abstract: A system and method for efficiently and accurately determining grating profiles uses characteristic signature matching in a discrepancy enhanced library generation process. Using light scattering theory, a series of scattering signatures vs. scattering angles or wavelengths are generated based on the designed grating parameters, for example. CD, thickness and Line:Space ratio. This method selects characteristic portions of the signatures wherever their discrepancy exceeds the preset criteria and reforms a characteristic signature library for quick and accurate matching. A rigorous coupled wave theory can be used to generate a diffraction library including a plurality of simulated diffraction spectrums based on a predetermined structural parameter of the grating. The characteristic region of the plurality of simulated diffraction spectrums is determined based on if the root mean square error of the plurality of simulated diffraction spectrums is larger than a noise level of a measuring machine.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: May 12, 2009
    Assignees: Industrial Technology Research Institute, Nanometrics Incorporated
    Inventors: Nigel Smith, Yi-sha Ku, Shih Chun Wang, Chun-hung Ko
  • Publication number: 20090116014
    Abstract: Overlay error between two layers on a substrate is measured using an image of an overlay target in an active area of a substrate. The overlay target may be active features, e.g., structures that cause the device to function as desired when manufacturing is complete. The active features may be permanent structures or non-permanent structures, such as photoresist, that are used define the permanent structures during manufacturing. The image of the overlay target is analyzed by measuring the light intensity along one or more scan lines and calculating a symmetry values for the scan lines. Using the symmetry values, the overlay error can be determined.
    Type: Application
    Filed: December 19, 2008
    Publication date: May 7, 2009
    Applicant: Nanometrics Incorporated
    Inventors: Nigel P. Smith, Kevin E. Heidrich
  • Patent number: 7515279
    Abstract: This disclosure provides methods for measuring asymmetry of features, such as lines of a diffraction grating. On implementation provides a method of measuring asymmetries in microelectronic devices by directing light at an array of microelectronic features of a microelectronic device. The light illuminates a portion of the array that encompasses the entire length and width of a plurality of the microelectronic features. Light scattered back from the array is detected. One or more characteristics of the back-scattered light may be examined by examining data from complementary angles of reflection. This can be particularly useful for arrays of small periodic structures for which standard modeling techniques would be impractically complex or take inordinate time.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: April 7, 2009
    Assignee: Nanometrics Incorporated
    Inventor: Christopher Raymond
  • Patent number: 7511293
    Abstract: Scatterometers and methods of using scatterometry to determine several parameters of periodic microstructures, pseudo-periodic structures, and other very small structures having features sizes as small as 100 nm or less. Several specific embodiments of the present invention are particularly useful in the semiconductor industry to determine the width, depth, line edge roughness, wall angle, film thickness, and many other parameters of the features formed in microprocessors, memory devices, and other semiconductor devices. The scatterometers and methods of the invention, however, are not limited to semiconductor applications and can be applied equally well in other applications.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: March 31, 2009
    Assignee: Nanometrics Incorporated
    Inventors: Chris Raymond, Steve Hummel
  • Patent number: 7508976
    Abstract: A diffraction based overlay metrology system produces the overlay error independent of effects caused by local process variations. Generally, overlay patterns include process variations that provide spectral contributions, along with the overlay shift, to the measured overlay error. The contributions from process variations are removed from the determined overlay error. In one embodiment, the local process variations are removed by measuring the overlay pattern before and after the top diffraction gratings are formed. A plurality of differential spectra from the measurement locations of the completed overlay pattern can then be used with a plurality of ratios of differential spectra from measurement locations of the incomplete overlay pattern can then be used to determine the overlay error by either direct calculation or by fitting techniques. In another embodiment, the local process variations are removed with no premeasurement but with careful construction of the overlay patterns.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: March 24, 2009
    Assignee: Nanometric Incorporated
    Inventors: Weidong Yang, Roger R. Lowe-Webb, Silvio J. Rabello
  • Patent number: 7504642
    Abstract: A method and apparatus uses photoluminescence to identify defects in one or more specified material layers of a sample. One or more filtering elements are used to filter out predetermined wavelengths of return light emitted from a sample. The predetermined wavelengths are selected such that only return light emitted from one or more specified material layers of the sample is detected. Additionally or alternatively, the wavelength of incident light directed into the sample may be selected to penetrate the sample to a given depth, or to excite only one or more selected material layers in the sample. Accordingly, defect data characteristic of primarily only the one or more specified material layers is generated.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: March 17, 2009
    Assignee: Nanometrics Incorporated
    Inventors: Steven G. Hummel, Tom Walker
  • Patent number: 7502101
    Abstract: Scatterometers and methods of using scatterometry to determine several parameters of periodic microstructures, pseudo-periodic structures, and other very small structures having features sizes as small as 100 nm or less. Several specific embodiments of the present invention are particularly useful in the semiconductor industry to determine the width, depth, line edge roughness, wall angle, film thickness, and many other parameters of the features formed in microprocessors, memory devices, and other semiconductor devices. The scatterometers and methods of the invention, however, are not limited to semiconductor applications and can be applied equally well in other applications.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: March 10, 2009
    Assignee: Nanometrics Incorporated
    Inventors: Chris Raymond, Steve Hummel, Sean Liu
  • Patent number: 7492467
    Abstract: Various embodiments include a metrology tool comprising an emitter configured to emit an incident light beam at a production substrate including an ARL, a receiver configured to receive a reflected light beam from the production substrate, a spectrometer configured to determine a digital signal representing an intensity of a wavelength within the reflected light beam, and a processor configured to determine a spectrum of the reflected light beam from the digital signal, select a suppression band based on an expected wavelength representative of a portion of the ARL, and determine a property of the ARL based on a portion of the spectrum in the selected suppression band.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 17, 2009
    Assignee: Nanometrics Incorporated
    Inventors: Ofer Du-Nour, Vladimir Rubinstein
  • Publication number: 20090040613
    Abstract: A structure that is located adjacent to a measurement target on a substrate is used to convert incident radiation from an optical metrology device to be in-plane with the measurement target. The structure may be, e.g., a grating or photonic crystal, and may include a waveguide between the structure and the measurement target. The in-plane light interacts with the measurement target and is reflected back to the structure, which converts the in-plane light to out-of-plane light that is received by the optical metrology device. The optical metrology device then uses the information from the received light to determine one or more desired parameters of the measurement target. Additional structures may be used to receive light that is transmitted through or scattered by the measurement target if desired.
    Type: Application
    Filed: August 7, 2007
    Publication date: February 12, 2009
    Applicant: NANOMETRICS INCORPORATED
    Inventor: Ye Feng
  • Patent number: 7477396
    Abstract: In systems and methods measure overlay error in semiconductor device manufacturing based on target image asymmetry. As a result, the advantages of using very small in-chip targets can be achieved, while their disadvantages are reduced or eliminated. Methods for determining overlay error based on measured asymmetry can be used with existing measurement tools and systems. These methods allow for improved manufacturing of semiconductor devices and similar devices formed from layers.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: January 13, 2009
    Assignee: Nanometrics Incorporated
    Inventors: Nigel Peter Smith, Yi-sha Ku, Hsiu-Lan Pang
  • Publication number: 20090010529
    Abstract: A method for processing wafers includes learning a first pattern at a de-skew site on a first wafer layer, saving the first patterns in a recipe for de-skewing wafers, learning a second pattern at the de-skew site a second wafer layer, and saving the second pattern in the same recipe for de-skewing wafers. Learning the first pattern may include determining a score of uniqueness for the first pattern. The method further includes finding the de-skew site on the second wafer layer using the first pattern before learning the second pattern. Finding the de-skew site includes determining a score of similarity between the first pattern and the second pattern. Learning the second pattern is performed when the score of similarity is less than a threshold value. A recipe for de-skewing wafers includes multiple patterns of a de-skew site of a wafer, wherein the patterns include a first pattern at the de-skew site on a first wafer layer and a second pattern at the de-skew site on a second wafer layer.
    Type: Application
    Filed: September 10, 2008
    Publication date: January 8, 2009
    Applicant: NANOMETRICS INCORPORATED
    Inventors: Jian Zhou, Hua Chu
  • Patent number: 7473502
    Abstract: A method of determining and correcting for distortions introduced by an imaging tool. The method includes providing an imaging tool having a field of view (FOV), and creating a target pattern containing a regular array of symmetric sub-patterns having locations spanning the FOV. Using the imaging tool, the method then includes measuring relative position of the sub-pattern images at one or more target orientations, determining tool-induced sub-pattern position deviations from designed locations of the sub-patterns, and applying corrections to compensate for an orientation independent component of the sub-pattern position deviations. The target pattern may be mounted on a stage of the measurement tool, created on a mask used in the lithographic process, or created on a wafer being measured by the measuring tool.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: January 6, 2009
    Assignees: International Business Machines Corporation, Nanometrics Incorporated
    Inventors: Chistopher P. Ausschnitt, Lewis A. Binns, Jennifer L. Morningstar, Nigel Smith
  • Patent number: 7469164
    Abstract: Various embodiments include a method for providing instructions to a process tool. The method includes emitting an incident light beam at a substrate, receiving a reflected light beam from the substrate and determining a spectrum of the reflected light beam. The method further includes determining a first property of a first layer of the substrate and a second property of a second layer of the substrate, based on the spectrum determination. The method further includes comparing the first property of the first layer to a first reference property and comparing the second property of the second layer to a second reference property. The method further includes determining the instructions based on the first property comparison and the second property comparison; and providing the instructions to the process tool.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: December 23, 2008
    Assignee: Nanometrics Incorporated
    Inventor: Ofer Du-Nour
  • Patent number: 7465590
    Abstract: A sample that is processed to remove a top layer, e.g., using chemical mechanical polishing or etching, is accurately measured using multiple models of the sample. The multiple models may be constrained based on a pre-processing measurement of the sample. By way of example, the multiple models of the sample may be linked in pairs, where one pair includes a model simulating the pre-processed sample and another model simulating the post-processed sample with a portion of the top layer remaining, i.e., under-processing. Another pair of linked models includes a model simulating the pre-processed sample and a model simulating the post-processing sample with the top layer removed, i.e., the correct amount of processing or over-processing. The underlying layers in the linked model pairs are constrained to have the same parameters. The modeling process may use a non-linear regression or libraries.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: December 16, 2008
    Assignee: Nanometrics Incorporated
    Inventors: Ye Feng, Zhuan Liu
  • Patent number: 7450225
    Abstract: A metrology system performs optical metrology while holding a sample with an unknown focus offset. The measurements are corrected by fitting for the focus offset in a model regression analysis. Focus calibration is used to determine the optical response of the metrology device to the focus offset. The modeled data is adjusted based on the optical response to the focus offset and the model regression analysis fits for the focus offset as a variable parameter along with the sample characteristics that are to be measured. Once an adequate fit is determined, the values of the sample characteristics to be measured are reported. The adjusted modeled data may be stored in a library, or alternatively, modeled data may be adjusted in real-time.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: November 11, 2008
    Assignee: Nanometrics Incorporated
    Inventors: Zhuan Liu, Yudong Hao, Ye Feng, Yongdong Liu