Patents Assigned to Nanya Technology Corporation
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Patent number: 11877442Abstract: The present disclosure provides a semiconductor memory device. The semiconductor memory device comprises a substrate, which includes a storage area and a peripheral area, wherein the storage area has a contact plug, a bit line structure adjacent to the contact plug, an air gap between the bit line structure and the contact plug, a barrier layer conformally overlaying the bit line structure, and a landing pad above the barrier layer, wherein the substrate includes a trench between the storage area and the peripheral area, the trench is filled with a nitride material, and the substrate further comprises a first oxide layer above the nitride material in the trench and on the landing pad, a nitride layer above the first oxide layer, and a second layer above the nitride layer.Type: GrantFiled: May 24, 2022Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Jr-Chiuan Wang, Rou-Wei Wang, Wei-Yu Chen
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Patent number: 11876000Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming an energy-sensitive layer over the target layer. The method also includes performing a first energy treating process to form a first treated portion in the energy-sensitive layer, and performing a second energy treating process to form a second treated portion in the energy-sensitive layer. The method further includes removing the first treated portion and the second treated portion to form a first opening and a second opening in the energy-sensitive layer, and transferring the first opening and the second opening into the target layer.Type: GrantFiled: December 14, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chia-Hsiang Hsu
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Patent number: 11876051Abstract: The present application discloses a conductive layer stack, a semiconductor device and methods for fabricating the conductive layer stack and the semiconductor device. The conductive layer stack includes an intervening layer comprising tungsten silicide and positioned on an under-layer; a filler layer comprising tungsten and positioned on the intervening layer. The under-layer comprises titanium nitride and comprises a columnar grain structure. A thickness of the intervening layer is greater than about 4.1 nm.Type: GrantFiled: January 12, 2022Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Che-Hsien Liao, Yueh Hsu
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Patent number: 11876077Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.Type: GrantFiled: March 12, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
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Patent number: 11876079Abstract: The provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die including a pad layer, forming a through-substrate opening along the second die and extending to the pad layer in the first die, conformally forming an isolation layer in the through-substrate opening, performing a punch etch process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer, performing an isotropic etch process to form a recessed space extending from the through substrate opening and in the pad layer, conformally forming a barrier layer in the through-substrate opening and the recessed space, and forming a filler layer in the through-substrate opening and the recessed space.Type: GrantFiled: November 24, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Shing-Yih Shih
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Patent number: 11876075Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the package structure; a bottom interior layer enclosed by the bottom exterior layer; and a cavity enclosed by the bottom interior layer.Type: GrantFiled: December 23, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chun-Heng Wu
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Patent number: 11877444Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a dielectric structure disposed over the substrate; a bit line bottom contact disposed in the dielectric structure; a composite decoupling structure disposed between the dielectric structure and the bit line bottom contact, wherein the composite decoupling structure comprises an air gap and a dielectric spacer; a bit line top contact disposed over the bit line bottom contact; and a bit line to disposed over the bit line top contact.Type: GrantFiled: January 26, 2022Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11876044Abstract: A method for activating a backup unit includes providing a fuse element connected to the backup unit. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. The method also includes applying a stress voltage on the drain region of the fuse element; accumulating electrons in a portion of the STI structure adjacent to the drain region; generating a conductive path through the drain region and the source region so that the fuse element is conductive; and activating the backup unit through the fuse element.Type: GrantFiled: March 10, 2022Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Yi-Ju Chen, Jui-Hsiu Jao
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Patent number: 11877455Abstract: The present disclosure provides a method for preparing a vertical memory structure with air gaps. The method includes providing a substrate; forming an impurity layer at an upper portion of the substrate; forming a semiconductor stack including a lower semiconductor pattern structure filling a recess on the substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate; forming a plurality of gate electrodes surrounding a sidewall of the semiconductor stack, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction; and forming a plurality of air gap structures disposed at outer sides of the plurality of gate electrodes respectively.Type: GrantFiled: November 30, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Yuan-Yuan Lin
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Patent number: 11876074Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the to package structure; and a cavity enclosed by the bottom exterior layer.Type: GrantFiled: December 23, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Yi-Hsien Chou
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Patent number: 11876063Abstract: A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.Type: GrantFiled: August 31, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Shing-Yih Shih
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Patent number: 11876024Abstract: The present disclosure provides a method of operating a benchmark device embedded on a semiconductor wafer. The method includes applying a first voltage to a first electrode of the benchmark device, and applying a second voltage to a second electrode of the benchmark device. The method further includes electrically isolating a first component of the benchmark device from a second component of the benchmark device through a disconnecting switch connected between the first component and the second component.Type: GrantFiled: October 8, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Yi-Ju Chen, Jui-Hsiu Jao
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Patent number: 11876072Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).Type: GrantFiled: September 2, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wei-Zhong Li, Yi-Ting Shih, Chien-Chung Wang, Hsih-Yang Chiu
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Patent number: 11876067Abstract: A semiconductor package includes a package substrate, a semiconductor chip and a plurality of bonding wires. The package substrate includes a connection pad. The semiconductor chip is disposed over the package substrate and includes a chip pad, a bonding pad, and a redistribution layer. The bonding pad is closer to a periphery of the semiconductor chip than the chip pad. The redistribution layer is connected between the chip pad and the bonding pad. The bonding wires are connected in parallel between the connection pad and the bonding pad.Type: GrantFiled: October 18, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Wu-Der Yang
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Patent number: 11876094Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate and concurrently forming a first semiconductor unit, a second semiconductor unit, and a third semiconductor unit in the substrate. The first semiconductor unit has a first insulating stack, the second semiconductor unit has a second insulating stack, and the third semiconductor unit has a third insulating stack; and thicknesses of the first insulating stack, the second insulating stack, and the third insulating stack are all different.Type: GrantFiled: November 15, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tse-Yao Huang
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Patent number: 11877435Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a first bit line on a substrate; a contact adjacent to the first bit line on the substrate, wherein a first distance between a top portion of the contact and the first bit line is less than a second distance between a lower portion of the contact and the first bit line; a dielectric layer, disposed conformally over the first bit line, the substrate, and the contact; and a first air gap, sealed by the dielectric layer and defined by the first bit line, the substrate and the contact.Type: GrantFiled: January 12, 2022Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Yao-Hsiung Kung
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Patent number: 11876045Abstract: The present disclosure provides a method for preparing a semiconductor device with a copper-manganese liner. The method includes forming an opening structure in a first dielectric layer, wherein the opening structure has a first portion, a second portion and a third portion disposed between and physically connecting the first portion and the second portion; forming a lining material lining the first portion and the second portion of the opening structure and completely filling the third portion of the opening structure, wherein the lining material includes copper-manganese (CuMn); filling the first portion and the second portion of the opening structure with a conductive material after the lining material is formed; and performing a planarization process on the lining material and the conductive material.Type: GrantFiled: March 22, 2023Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chin-Ling Huang
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Patent number: 11875994Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first energy-sensitive patterns over the target layer. The method also includes forming a lining layer conformally covering the first energy-sensitive patterns. A first opening is formed over the lining layer and between the first energy-sensitive patterns. The method further includes filling the first opening with a second energy-sensitive pattern, and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, and the second openings and the third opening have different depths.Type: GrantFiled: January 7, 2022Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chih-Tsung Wu
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Patent number: 11876025Abstract: The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a wafer and a test structure disposed on the wafer. The test structure includes a first device having a first source/drain layer and a first gate layer disposed above the first source/drain layer; a second device, having a second source/drain layer and a second gate layer disposed above the second source/drain layer, the second gate layer connected to the first gate layer; a third device, disposed adjacent to the first device and having a third source/drain layer. The first gate layer is disposed above the third source/drain layer, and the first gate layer is disposed along a first direction and the second gate layer is disposed along a second direction orthogonal to the first direction.Type: GrantFiled: November 30, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Tsang-Po Yang
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Patent number: 11854832Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture. The profile modifier is disposed within the aperture to modify a profile of the aperture in a plan view. The contact feature is disposed within the aperture.Type: GrantFiled: February 7, 2022Date of Patent: December 26, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Shih-En Lin, Jui-Lin Chin
