Patents Assigned to National Semiconductor Corp.
  • Patent number: 6407618
    Abstract: An electronic circuit generates a bias current that is proportional to a frequency of a reference clock signal in a switched capacitor circuit. The electronic circuit includes a capacitive circuit selectively coupled to a transistor supplied by a voltage reference circuit. During a first phase the capacitive circuit is charged by a current from the transistor, and during the second phase the capacitive circuit is discharged to ground. The duration of each phase is related to the reference clock signal. The average current corresponds to a bias signal and is filtered to reduce ripple in the bias signal before the bias signal is received by the switched capacitor circuit. The capacitive circuit is configured with a first and second capacitor arranged in a complimentary out-of-phase configuration. During a first phase, the first capacitor is charged and the second capacitor is discharged. During the second phase, the second capacitor is charged and the first capacitor is discharged.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: June 18, 2002
    Assignee: National Semiconductor Corp.
    Inventors: Robert Callaghan Taft, Maria Rosaria Tursi
  • Patent number: 6342424
    Abstract: A high-Q spiral inductor structure that utilizes a three-layer substrate, and methods of manufacturing the structure, are provided. The three-layer substrate is utilizable for CMOS circuits while at the same time minimizing eddy current induction and increasing the inductor quality factor Q of the structure.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: January 29, 2002
    Assignee: National Semiconductor Corp.
    Inventor: Christoph Pichler
  • Patent number: 6281706
    Abstract: An output buffer circuit includes multiple programmable boost drive stages which allow selection of one of several drive strengths to accommodate a range of output load conditions, thereby achieving low noise and low power dissipation. In one embodiment, one or more of the boost circuits turn on after the primary driver circuit is turned on, and turn off before the primary circuit is turned off, thereby achieving soft turn-on and turn-off.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: August 28, 2001
    Assignee: National Semiconductor Corp.
    Inventors: Joseph D. Wert, Dan E. Daugherty, Richard L. Duncan
  • Patent number: 6249044
    Abstract: A light shield is provided for light sensitive flip chip integrated circuits. The flip chip includes an under bump layer to portions of which solder bumps are attached. A separate portion of this under bump layer is used to provide the light shield. The light shield excludes ambient light from the most light sensitive portions of the circuit so that the electrical characteristics of the flip chip integrated circuit are not significantly altered when the flip chip is operated in ambient light.
    Type: Grant
    Filed: June 17, 1999
    Date of Patent: June 19, 2001
    Assignee: National Semiconductor Corp.
    Inventors: Pai-Hsiang Kao, Nikhil Vishwanath Kelkar
  • Patent number: 6245491
    Abstract: Acid diffusion induced critical dimension change in a chemically amplified photoresist process is suppressed by lowering the reaction activation energy barrier. Energy required to overcome the reaction activation energy barrier is provided directly to the chemical bonds that are involved in the chemical reactions, rather than providing energy solely by thermal heating, thereby significantly increasing reaction rate without increasing acid diffusion.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: June 12, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Xuelong Shi
  • Patent number: 6246100
    Abstract: A thermal coupler utilizes Peltier heating and cooling to transmit a thermal signal across an electrical isolation barrier. Application of a potential difference across a thermal emitter in the form of a first pair of parallel strips of electrically conducting materials separated by a second electrically conducting material results in a temperature difference arising at junctions between the first electrically conducting material and the second electrically conducting material. This temperature difference is propagated across the electrical isolation barrier to a similar thermal detector structure lacking an applied voltage and possessing a second pair of junctions. Differential heating of the second pair of junctions of the thermal detector creates a Seebeck voltage in the thermal detector. This Seebeck voltage is amplified and processed as a communication signal.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: June 12, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Richard J. Strnad
  • Patent number: 6242348
    Abstract: Process for forming a boron-doped silicon gate layer underlying a cobalt silicide layer that reduces the risk of grooving and agglomeration of cobalt silicide layer, as well as boron penetration into a gate oxide layer. The process includes providing a PMOS transistor structure that includes an N-well on a P-type silicon substrate, a gate oxide layer and a silicon gate layer. Next, a cobalt layer is deposited on the PMOS transistor structure, which is then subjected to a first thermal treatment to form a bilayer CoSi/silicon stack structure. After removing unreacted cobalt, boron dopant (BF2+ or B+) and nitrogen ions (N2+) are implanted into the bilayer CoSi/silicon stack structure. The bilayer CoSi/silicon stack structure, implanted boron and implanted nitrogen are then subjected to second thermal treatment to form a CoSi2 layer on the silicon gate layer and to thermally activate the implanted boron.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: June 5, 2001
    Assignee: National Semiconductor Corp.
    Inventors: Abu-Hena Mostafa Kamal, Amjad Obeidat
  • Patent number: 6237074
    Abstract: A pipelined processor in which the decoder can consume a portion of an instruction and hold that portion in sub-field shadow registers while retrieving the remainder of the instruction in a subsequent cycle or cycles. Each byte in a prefetch buffer is individually tagged such that the decoder can clear individual bytes in the prefetch buffer in order to allow additional instruction bytes to be prefetched before the current instruction is completely consumed and decoded by the decode stage. This allows for an optimal buffer size that is less than the maximum possible instruction length but large enough to hold a complete copy of the vast majority of instructions.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: May 22, 2001
    Assignee: National Semiconductor Corp.
    Inventors: Christopher E. Phillips, Robert J. Divivier, Mario Nemirovsky
  • Patent number: 6233033
    Abstract: The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: May 15, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Paul McKay Moore
  • Patent number: 6225181
    Abstract: A bipolar transistor is vertically isolated from underlying silicon by an isolation layer of conductivity type opposite that of the collector. This isolation layer lies beneath the heavily doped buried layer portion of the collector, and is formed either by ion implantation prior to epitaxial growth of well regions, or by high energy ion implantation into the substrate prior to formation of the well and the heavily doped buried collector layer. Utilization of trench lateral isolation extending into the semiconductor material beyond the isolation layer permits blanket implant of the isolation layer, obviating the need for an additional masking step.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: May 1, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Haydn James Gregory
  • Patent number: 6218317
    Abstract: Disclosed are multilevel interconnects for integrated circuit devices, especially copper/dual damascene devices, and methods of fabrication. Methylated-oxide type hardmasks are formed over polymeric interlayer dielectric materials. Preferably the hardmasks are materials having a dielectric constant of less than 3 and more preferably 2.7 or less. Advantageously, both the hardmask and the interlayer dielectric can be spincoated.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: April 17, 2001
    Assignee: National Semiconductor Corp.
    Inventors: Sudhakar Allada, Chris Foster
  • Patent number: 6218884
    Abstract: An apparatus including a low voltage differential signaling (LVDS) driver circuit with on-resistance cancellation, includes a current steering circuit having an on-resistance. In order to cancel the on-resistance of the current steering circuit, the LVDS driver circuit also includes a current proportional to absolute temperature current source, a transistor having an on-resistance proportional to the on-resistance of the current steering circuit, and a voltage-to-current conversion circuit coupled to the transistor, wherein the voltage-to-current conversion circuit converts the drain-to-source voltage of the transistor into a current proportional to an output current of the LVDS driver circuit. A first resistive circuit receives the current proportional to absolute temperature and the current proportional to an output current of the LVDS driver circuit and in accordance therewith provides a first reference signal.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: April 17, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Kwok Fu Chiu
  • Patent number: 6214721
    Abstract: The present invention provides a “built-in” wave dampening, antireflective thin-film layer in a copper dual damascene film stack that reduces the standing wave intensity in the deep-UV photoresist. This is accomplished by depositing optically customized silicon/oxide/nitride films during dual damascene processing. In particular, one or more silicon nitride layers are replaced with a light absorbing silicon oxynitride film to provide built-in dampening layers. The silicon oxynitride stack can be densified by heat treatments to minimize electrical leakage concerns, if any. The invention eliminates the need for adding extra thin-film stacks during deep-UV photoprocessing.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: April 10, 2001
    Assignee: National Semiconductor Corp.
    Inventors: Joseph J. Bendik, Jr., Jeffrey R. Perry
  • Patent number: 6208094
    Abstract: A multiplexed video amplifier circuit includes a video preamplifier and a bias/brightness circuit the output of both being coupled to a switch. The video preamplifier provides a video signal, the bias/brightness circuit provides a DC bias signal, and the switch selectively couples to the output of either the video preamplifier or the bias/brightness circuit. In this way, the switch alternately receives the video signal and the DC bias signal and combines them to provide a single multiplexed video signal with both video and DC bias signal data. This multiplexed video signal is sent to a clamp amplifier and a video amplifier, both of which compare the magnitude of the multiplexed video signal with a reference signal. When the magnitude of the multiplexed video signal transcends the reference signal in a first direction, for example is lower than the reference signal, the clamp amplifier provides the DC bias signal to an external circuit.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: March 27, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Andy Morrish
  • Patent number: 6208215
    Abstract: A VCO and filter each include a variable transconductance amplifier as a resistive element. The same control bias current is supplied to the variable transconductance amplifier of both the oscillator and filter. This control bias current may be externally supplied, or may be generated on-chip from a thermal RC network formed from base-emitter junctions of bipolar transistors arrayed in single crystal silicon about a heat source. Application of a clock signal from the VCO to the heat source generates a heat pulse which propagates across the arrayed transistors. The resulting change in temperature produces a change in Vbe of the arrayed transistors. The phase shift between the original clock signal and the changed Vbe is determined solely by the time constant &tgr; of the particular thermal RC network. This time constant is a function of the inherent stable thermal resistance and capacitance of the single crystal silicon, and of the location and relative spacing of the arrayed transistors.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: March 27, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Don Sauer
  • Patent number: 6205501
    Abstract: A method and apparatus for performing a control transfer on a Universal Serial Bus (USB) device. A USB device includes a memory space for reading and writing data transmitted over a USB network. The memory space is shared between a plurality of endpoints. A host initiates a control transfer by transmitting a SETUP token to a first endpoint. The endpoint must accept the SETUP token. If the first endpoint does not expect the SETUP token, or if another endpoint is active, the device stores the token until a buffer is allocated and the first endpoint is made active.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: March 20, 2001
    Assignee: National Semiconductor Corp.
    Inventors: David Brief, David J. Fensore, Kent Bruce Waterson, Gregory Lewis Dean
  • Patent number: 6205511
    Abstract: A buffer manager divides a memory space into a plurality of buffers. Each buffer occupies a plurality of sequential memory locations. The sequential memory locations include a start and an end address. To write data to a buffer, the buffer manager provides a start address and burst size to an address translator. The address translator converts the start address and the burst size to SDRAM memory address locations. The start and end address of each buffer is mapped to a different bank in the SDRAM memory.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: March 20, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Sheung-Fan Wen
  • Patent number: 6201377
    Abstract: A match-insensitive low current bias circuit uses a transistor arrangement which takes advantage of the transistors' collector current degeneration, current gain through emitter sizing, and voltage gain to minimize any errors caused by stage mismatches created during production. The bias circuit of the present invention is particularly suited to integrated circuit applications where a low biasing current is required.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: March 13, 2001
    Assignee: National Semiconductor Corp.
    Inventor: Don R. Sauer
  • Patent number: 6198722
    Abstract: A method is shown for a central node to flow control one or more end stations operating under a medium access control protocol wherein the central node transmits a signal to the end stations that causes the end stations to defer a data transmission, and wherein the central node halts the transmission to reset a protocol timer in the end stations, and wherein the central node resumes transmission before expiration of another protocol timer that would cause the end stations to commit to attempting a data transmission onto the communications medium and the end stations can thereby be held in a flow control state without loss of transmission packets.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: March 6, 2001
    Assignee: National Semiconductor Corp.
    Inventor: William Bunch
  • Patent number: 6190936
    Abstract: A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) performing alloy/sintering of the metal-silicon interface prior to a chemical mechanical polish of the intermetal dielectric before the reflective metal electrode is formed; 2) chemical-mechanical polishing the intermetal dielectric layer again after vias are formed; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: February 20, 2001
    Assignee: National Semiconductor Corp.
    Inventors: Paul McKay Moore, Kevin Carl Brown, Richard Luttrell