Patents Assigned to National Semiconductor Corporation
  • Method and apparatus for achieving galvanic isolation in package having integral isolation medium
    Patent number: 8674418
    Abstract: An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: March 18, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Anindya Poddar, Vijaylaxmi Khanolkar, Ashok S. Prabhu, Peter Johnson
  • Non-volatile memory cell having a heating element and a substrate-based control gate
    Patent number: 8669157
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: March 11, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Laser diode / LED drive circuit
    Patent number: 8665188
    Abstract: The invention relates to an apparatus for controlling the output of an LD or LED. The apparatus includes a substantially static bias source and a variable source. The substantially static bias source provides a bias current to the LD/LED. The variable source is capacitively coupled to the LD/LED. The bias current may be provided such that it is higher than a threshold current at which, when provided to an LD, lasing occurs.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: March 4, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Yeong Ryong Yun
  • ?-? difference-of-squares RMS to DC converter with multiple feedback paths
    Patent number: 8665127
    Abstract: Architectures of ?? difference-of-squares RMS-to-digital converters employing multiple feedback paths. Additional feedback paths enable a stable ?? closed-loop behavior in different topologies where the RMS level of the quantization error processed by the squaring non-linearity is minimized. Such feedback paths include lowpass filtered and constant gain feedback paths, lowpass and highpass filtered paths or multiple lowpass filtered paths. These can be combined with multiple integrators in the forward path, with frequency compensation provided by additional feedforward or feedback paths. Electronic configurability can further extend the total input referred dynamic range (DR) of such architectures.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: March 4, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Paulo Gustavo Raymundo Silva
  • Sigma-delta difference-of-squares log-RMS to DC converter with forward path multiplier and chopper stabilization
    Patent number: 8665128
    Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter for true RMS detection by merging a ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares. Chopper-stabilization, implemented through commutators running at two different frequencies, can be employed to reduce sensitivity to DC offsets and low-frequency errors, resulting in an extension of the useful input-referred dynamic range. High-order ?? LOG-RMS converters can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The resulting implementations are ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: March 4, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Paulo Gustavo Raymundo Silva, Michael Hendrikus Laurentius Kouwenhoven
  • ?? difference-of-squares LOG-RMS to DC converter with forward and feedback paths signal squaring
    Patent number: 8665126
    Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter” by merging a traditional ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares concept. Two basic architectures include one based on two squaring cells in the feedforward and feedback paths and a second based on a single squaring cell in the forward path. High-order ?? LOG-RMS can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The embodiments as described allow the implementations of ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: March 4, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Paulo Gustavo Raymundo Silva, Michael Hendrikus Laurentius Kouwenhoven
  • Semiconductor structure with galvanic isolation
    Patent number: 8659149
    Abstract: Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: February 25, 2014
    Assignee: National Semiconductor Corporation
    Inventors: William French, Peter J. Hopper, Ann Gabrys
  • GROWTH OF MULTI-LAYER GROUP III-NITRIDE BUFFERS ON LARGE-AREA SILICON SUBSTRATES AND OTHER SUBSTRATES
    Publication number: 20140051226
    Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.
    Type: Application
    Filed: October 22, 2013
    Publication date: February 20, 2014
    Applicant: National Semiconductor Corporation
    Inventors: Sandeep R. BAHL, Jamal RAMDANI
  • Universal chip carrier and method
    Patent number: 8650748
    Abstract: A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: February 18, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Artur Darbinyan, David T. Chin, Kurt E. Sincerbox
  • GROWTH OF MULTI-LAYER GROUP III-NITRIDE BUFFERS ON LARGE-AREA SILICON SUBSTRATES AND OTHER SUBSTRATES
    Publication number: 20140042458
    Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.
    Type: Application
    Filed: October 22, 2013
    Publication date: February 13, 2014
    Applicant: National Semiconductor Corporation
    Inventors: Sandeep R. BAHL, Jamal RAMDANI
  • Method and apparatus for dicing die attach film on a semiconductor wafer
    Patent number: 8647966
    Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a die attach film, an adhesive and a base film. The die attach film is cut with the sawing blade. During the cutting operation, a contact portion of the sawing blade engages one of the layers and moves at least partly in one direction. While the contact portion of the sawing blade engages the layer, the support structure moves in the opposite direction. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: February 11, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Ken Fei Lim, You Chye How, Kooi Choon Ooi
  • ESD CLAMP WITH AUTO BIASING UNDER HIGH INJECTION CONDITIONS
    Publication number: 20140034996
    Abstract: In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions.
    Type: Application
    Filed: October 9, 2013
    Publication date: February 6, 2014
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Vladislav Vashchenko
  • Methods for manufacturing a radio frequency identification tag without aligning the chip and antenna
    Patent number: 8635762
    Abstract: A method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having asymmetrical interconnect system for one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and “L” shaped gold-bumped holes can be arranged on the same side of the ship in an opposing action, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads. Alternatively, a pair of poles can be located on opposing chips surfaces, such that antenna substrates can be attached to both the top and bottom of the chip to form a product “sandwich”, whereby the rotational orientation of the chip is irrelevant at an antenna attachment step.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: January 28, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Nikhil V. Kelkar, Sadanand R. Patil, Cheol Hyun Han
  • Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling common mode voltage at input
    Patent number: 8633756
    Abstract: Low voltage differential signaling (LVDS) circuitry and method for dynamically controlling the common mode voltage at the input of an LVDS receiver. The common mode voltage of the incoming LVDS signal is monitored. The common mode voltage at the input of the LVDS receiver is clamped at a clamp voltage when the common mode voltage of the incoming LVDS signal is less than a predetermined voltage, and allowed to track it otherwise.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: January 21, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Arlo J. Aude, Soumya Chandramouli
  • Enhancement-mode GaN MOSFET with low leakage current and improved reliability
    Patent number: 8624260
    Abstract: An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.
    Type: Grant
    Filed: January 30, 2010
    Date of Patent: January 7, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Jamal Ramdani
  • High step-up ratio soft-switched flyback converter
    Patent number: 8605467
    Abstract: A converter circuit includes a transformer having a first side and a second side. The converter circuit also includes a switch coupled to the first side of the transformer. The converter circuit further includes a rectifying diode coupled to the second side of the transformer and to a first output terminal of the converter circuit. In addition, the converter circuit includes a clamping diode coupled to the second side of the transformer, to the rectifying diode, and to a second output terminal of the converter circuit. The converter circuit may include a boost section and a flyback section. The converter circuit may also include an active clamp and an isolated flyback section.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: December 10, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Giovanni Frattini, Giorgio Spiazzi, Paolo Mattavelli
  • Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates
    Patent number: 8592292
    Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: November 26, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Sandeep R. Bahl, Jamal Ramdani
  • Heart monitoring system or other system for measuring magnetic fields
    Patent number: 8591427
    Abstract: A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 26, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Lawrence H. Zuckerman, Michael X. Maida, Dennis M. Monticelli, James B. Wieser, Jamal Ramdani, Paul Mawson, Moulay Mohamed Ibourk
  • Instantaneous average current measurement method
    Patent number: 8587275
    Abstract: Circuitry and method for providing a signal indicative of instances of conduction of average inductor current in a DC-to-DC voltage converter. Such signal identifies a time when the instantaneous average current being conducted by the inductor in a DC-to-DC voltage converter can be measured by providing a signal edge approximately halfway through one of the increasing and decreasing current conduction intervals of the inductor.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: November 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Faruk Jose Nome Silva, Karen Chan
  • System and method for providing an active current assist with analog bypass for a switcher circuit
    Patent number: 8587268
    Abstract: A system and method are disclosed for providing an active current assist with analog bypass for a switcher circuit. An active current assist circuit is coupled to a buck regulator circuit, which includes a switcher circuit, an inductor circuit and a capacitor circuit. The active current assist circuit includes an active current analog bypass control circuit and a current source. The active current analog bypass control circuit receives and uses current limit information, voltage error information, and drop out information to determine a value of assist current that is appropriate for a current operational state of the buck regulator circuit. The active current analog bypass control circuit causes the current source to provide the appropriate value of assist current to the buck regulator circuit.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: November 19, 2013
    Assignee: National Semiconductor Corporation
    Inventor: Jeffry Mark Huard