Abstract: Described herein is technology for, among other things, input bias current cancellation. The technology includes a bipolar differential pair coupled with a supply voltage (VCC). The bipolar differential pair includes a first transistor and a second transistor. The technology further includes an input bias current cancellation circuit coupled with the bipolar differential pair and including a third transistor. The third transistor has a collector-emitter voltage VCE, and the bipolar differential pair is operable to receive an input voltage greater than VCC?2VCE without causing the third transistor to operate in the saturation region.