Abstract: In a layout design of a semiconductor circuit, by selecting a frequently-used layout cell based on a layout design, a common location (coordinate) at which dummy metal is arranged is specified. A new layout cell in which dummy metal is arranged in advance at the specified arrangement location is generated. Dummy metal is arranged by replacing the frequently-used layout cell from which the new layout cell is generated by the new layout cell having dummy metal or by overlapping them. Thus, process such as wiring correction in which the amount of data depends on processing speed can be carried out by use of the inexpensive computer having low throughputs and the small amount of memory.

Abstract: A driving circuit of the display unit includes a driving circuit including a read only memory and a rewritable nonvolatile memory. The rewritable nonvolatile memory stores display quality specifying information for specifying the display quality of a display panel connected to the driving circuit. The read only memory stores the display quality initial information used for initialization of the display quality of an optional display panel. By preferentially using the information stored in the rewritable nonvolatile memory, it is possible to drive the display panel at an optimum display quality in the normal state. Moreover, even when it is impossible to normally read data from the rewritable nonvolatile memory, it is possible to drive the display panel at an initial-state display quality by using the data in the read only memory.

Abstract: A communication device includes a current information storage unit 130 that stores the bit boundary signal at each of timings at which a sampling clock is updated, a past information storage unit 140 that takes in and stores a signal stored in the current information storage unit 130 when a variation point of a reception signal is detected, and does not update a signal stored therein when no variation point of the reception signal is detected, and a clock selection unit 44 that selects CLKSEL2 used for the sampling of the reception signal from N-phase clocks based on a signal stored in the current information storage unit 130 when a variation point of the reception signal is detected, and selects CLKSEL3 based on a signal stored in the past information storage unit 140 when no variation point of the reception signal is detected.

Abstract: Provided are a probe card including a first area group including a plurality of first areas, each including a plurality of probes for input pad and probes for output pad, the first areas being aligned in L rows by M columns (L, M: natural number); and a second area group including a plurality of second areas, each including a plurality of probes for input pad, the second areas being aligned in (L×N) rows by M columns (N: natural number); and the first area group and the second area group are continuously connected in a column direction according to the chip alignment, such that the first areas and the second areas are aligned in {L+(L×N)} rows by M columns.

Abstract: A resistor string type D/A converter in accordance with an exemplary aspect of the present invention includes a resistor string, switches, a higher-order decoder, a lower-order decoder, and a conversion unit. The resistor string generates a plurality of analog voltages by dividing a voltage between a first reference voltage and a second reference voltage. Each of the switches is provided for a respective one of a plurality of voltage drawing points. The higher-order decoder generates a higher-order control signal according to the value of higher bits of an input digital signal. The lower-order decoder generates a lower-order control signal corresponding to the value of lower bits of the input digital signal. The conversion unit outputs a voltage between a pair of the analog voltage values obtained through a pair of switches based on the lower-order control signal.

Abstract: In a large capacity semiconductor storage device having a multi-bank configuration, it is desired to reduce a peak current of one refresh operation, to avoid an interference between adjacent banks, and to prevent a data breaking of a memory cell caused by a lack of a data hold time. A semiconductor storage device includes: a memory cell array part including a plurality of banks; a refresh control circuit configured to output a refresh timing control signal periodically; and an access control circuit configured to perform a refresh operation on a group of banks which are not adjacent to one another in accordance with a preset combination of banks which are simultaneously activated and a preset activating order when the refresh timing control signal is supplied.

Abstract: Provided is a protection circuit that is connected between a power supply terminal and an output terminal, and turns off an output transistor when an abnormality occurs in a system, the output transistor outputting a current to a load connected to the output terminal, the protection circuit including: a first discharge unit that is connected between a gate electrode of the output transistor and the power supply terminal, and discharges an electric charge of the gate electrode until a potential of the gate electrode becomes equal to a power supply potential, when an abnormality occurs in the system, and a second discharge unit that is connected between the gate electrode and a source electrode of the output transistor, and discharges the electric charge of the gate electrode until the potential of the gate electrode becomes equal to an output potential, when an abnormality occurs in the system.

Abstract: An input circuit, includes a first buffer circuit whose output is couple to an output signal terminal of the input circuit, and whose input is coupled to an input signal terminal of the input circuit, a second buffer circuit, a third buffer circuit, a first differential amplification circuit whose first input is coupled to a first external power source terminal, whose second input is coupled to an output of the second buffer circuit, and whose output is coupled to an input of the second buffer circuit, a second differential amplification circuit whose first input is coupled to a second external power source terminal, whose second input is coupled to an output of the third buffer circuit, and whose output is coupled to an input of the third buffer circuit, a first resistance whose one end is coupled to the output of the first differential amplification circuit, and whose another end is coupled between the input signal terminal of the input circuit and the input of the first buffer circuit, a second resistance

Abstract: A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole.

Abstract: An embodiment of the present invention provides a video signal multiplexing apparatus including a separator separating picture information and additional information from a received video signal, a controller adjusting, if the picture information is out of sync with the additional information, a data amount of the additional information based on a data amount of the picture information in such a manner that the picture information is in sync with the additional information, and a multiplexer multiplexing the encoded data and the additional information the data amount of which has been adjusted.

Abstract: A semiconductor device including an electrostatic discharge element that protects the semiconductor device from electrostatic destruction is provided. The semiconductor device includes a first circuit, a second circuit, a connection node connecting the first node to the second node, and a first inductor connected between the connection node and a first power supply. The first inductor and the electrostatic discharge element are formed so that they vertically overlap each other.

Abstract: A display apparatus includes a delay generation circuit that generates a reference signal and a competing signal, the competing signal being generated based on a delay set signal, an input order judgment circuit that judges an input order of the reference signal and the competing signal, a delay set circuit that generates the delay set signal based on a judgment result in the input order judgment circuit, and an internal synchronous control circuit that controls transfer of display data between a CPU and a display panel. An operation test of the internal synchronous control circuit is performed using the reference signal and the competing signal. Hence, fault coverage can be enhanced.

Abstract: A display control circuit in accordance with an exemplary aspect of the present invention is including a display memory that stores display data to be displayed on a display device, the display memory being supplied with electric power through a power-supply terminal, a power-supply unit that connects the power-supply terminal to a power-supply or a ground according to a request, and a control unit that requests the power-supply unit to connect the power-supply terminal to a ground when the display memory enters a standby mode in which no displaying is performed on the display device, and requests the power-supply unit to connect the power-supply terminal to a power supply when a predetermined time has elapsed after the request even if the display memory is in the standby mode.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: In order to reduce the number of electrodes included in test patterns, the semiconductor integrated circuit includes, a plurality of first and second chains, a first common electrode connected to one end of each first chain, a second common electrode connected to one end of each second chain, and a plurality of selection electrodes. Each selection electrode is connected to the other end of any one of the plurality of first chains and to the other end of any one of the plurality of second chains. When a test target chain is selected from the plurality of first chains, a first reference voltage is applied to the first common electrode, a second reference voltage is applied to a target selection electrode that is connected to the test target chain, and a current flowing in the target selection electrode is measured to obtain a resistance value of the test target chain.

Abstract: A semiconductor integrated circuit device includes: terminals 11a and 11m; first to (2n+1)-th resistive elements (n is an integer of at least 1) (resistive element group 12) connected in series between the terminals 11a and 11m; a selection circuit 14 selecting, assuming that a terminal 11a connected to one end of the first resistive element is a 0th node, a terminal 11m connected to the other end of the (2n+1)-th resistive element is a (2n+1)-th node, and a connection point of the other end of an i-th resistive element (i is an integer from 1 to 2n) and one end of an (i+1)-th resistive element is an i-th node, any one of the 0th to (2n+1)-th nodes and outputting a voltage applied to the selected node; a switch group 15a capable of shorting any 2k-th node (k is an integer from 0 to n); and a switch group 15b capable of shorting any (2k+1)-th node. The 2k-th and (2k+1)-th nodes are shorted, and subsequently, a predetermined voltage is temporarily applied between the terminals 11a and 11m.

Abstract: A signal transfer circuit according to the present invention includes a differential signal generation unit that generates a differential signal according to a voltage difference between two input signals, a voltage difference detection unit that detects a voltage difference between the two input signals input to the differential signal generation unit, and a signal output unit that outputs a signal including a predetermined value if the voltage difference is not detected by the voltage difference detection unit, and outputs the differential signal generated by the differential signal generation unit if the voltage difference is detected by the voltage detection unit.

Abstract: A differential chopper comparator compares an input signal voltage and a first voltage, and includes a first capacitor, a second capacitor, and a differential amplification unit including a differential amplification circuit. Either the input signal voltage or the first voltage is applied to one end of the first capacitor via a first switch unit. A fixed voltage is applied to one end of the second capacitor via a second switch unit. Either a non-inverting input terminal or an inverting input terminal of the differential amplification circuit is connected to the other end of the first capacitor, and the other terminal is connected to the other end of the second capacitor. An impedance of the first switch unit side viewed from one end of the first capacitor and an impedance of the second switch unit side viewed from one end of the second capacitor are substantially same.

Abstract: A manufacturing method of a semiconductor device includes: forming a wiring in a first interlayer insulating layer in a first region; etching an surface portion of the first interlayer insulating layer in a second region; forming a plurality of opening portions extended below in the etched region; and forming a lower electrode layer, a dielectric layer, and a common upper electrode in each of the plurality of opening portions to form a plurality of capacitance portions. The step of forming the plurality of capacitance portions, includes: forming the common upper electrode so that an upper surface of the first interlayer insulating layer and an upper surface of the common upper electrode approximately lie in the same plane.

Abstract: A lead frame includes a die pad on which at least one IC chip is mounted, a plurality of leads that electrically connect the IC chip and at least one external element, and a plurality of projections that are formed in at least one edge of the die pad. The projections are used as at least one bonding point that connect with at least one free terminal of the IC chip or as references of positioning when the IC chip is arranged on the die pad.