Abstract: A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.

Abstract: An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

Abstract: The MOS device with resistive field plate for realizing conductance modulation field effect in the present invention is based on the existing trench gate MOS device, and a semi-insulating resistive field plate electrically connected to the trench gate structure and the drain structure is added in the drift region, where the trench gate structure can control the on-off of the MOS channel, and the semi-insulating resistive field plate can adjust the doping concentration of the drift region to modulate the conductance of the on-state drift region and the distribution of off-state high-voltage blocking electric field, thus a lower on-resistance can be obtained. In addition, the modern 2.5-dimensional processing technology based on deep trench etching is adopted in the present invention, which is conducive to the miniaturization design and high density design of the structure and is more suitable for the More than Moore (beyond Moore) development of modern integrated semiconductor devices.

Abstract: A shared-dielectric MOSFET device with a resistive-field-plate and a preparation method are provided. In the shared-dielectric MOSFET device, the semi-insulating resistive-field-plate electrically connected to the trench gate structure and the drain structure is introduced in the drift region of the existing trench gate MOS devices, and when the trench gate structure controls the MOS channel to be turned on or turned off, the semi-insulating resistive-field-plate can adjust the doping concentration of the drift region, to modulate the conductance of the on-state drift region and the distribution of a off-state high-voltage blocking electric field, thereby obtaining a lower on-resistance. Meanwhile, in the preparation method of the present disclosure, the modern 2.

Abstract: A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.

Abstract: The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.

Abstract: A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.

Abstract: An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

Abstract: A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.

Abstract: A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.

Abstract: A differential-follower control circuit has been provided, comprising: a follower; an output-voltage following module, which controls a voltage at a control terminal of the follower to vary with an output voltage; a substrate-voltage following module, which controls a substrate voltage of an output transistor of the follower to vary with an input voltage; an output terminal of the follower is connected to a first terminal of the output-voltage following module; a second terminal of the output-voltage following module is connected to the control terminal of the follower; a first terminal of the substrate-voltage following module is connected to an input terminal of the follower and a second terminal of the substrate-voltage following module is connected to a substrate of the output transistor; the invention effectively improves the overall linearity of the follower.

Abstract: The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.

Abstract: A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

Abstract: A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.

Abstract: SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.

Abstract: A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

Abstract: The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents, and when the oscillating circuit is used to provide clock signals for the sensor, it can be integrated with a sensor signal processing circuit to realize the miniaturization and integration of the sen

Abstract: A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.

Abstract: SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.

Abstract: The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents.