Abstract: Doped semiconductor nanoparticles of a size (<100 Å) which exhibit quantum effects. The nanoparticles are grown and doped within a polymer matrix.

Abstract: Apparatus and method for insuring data cache content integrity among parallel processors is provided. Each processor has a data cache to store intermediate calculations. The data cache of each processor is synchronized with each other through the use of synchronization intervals. During entry of a synchronization interval, modified data variables contained in an individual cache are written back to a shared memory. The unmodified data contained in a data cache is flushed from memory. During exiting of a synchronization interval, data variables which were not modified since entry into the synchronization interval are also flushed. By retaining modified data cache values in the individual processors which computed the modified values, unnecessary access to shared memory is avoided.

Abstract: High speed and high drive BiCMOS buffers, inverters, and gates receiving synchronous differential inputs are provided having at least two npn bipolar transistors and at least one nMOS transistor. The first bipolar transistor has a base receiving a noninverting input, a collector coupled to the high voltage rail, and an emitter coupled to the circuit output. In several embodiments, the second bipolar transistor has its collector coupled to the emitter of the first bipolar transistor, its emitter coupled to ground, and its base coupled to the source of an nMOS transistor which is receiving the inverting input at its gate. In these embodiments, the output is taken from the emitter of the first bipolar transistor and the collector of the second bipolar transistor with the first bipolar transistor pulling up when the input is high, and the second bipolar transistor pulling down when the input is low.

Abstract: A power integrated circuit includes a substrate with an overlying epitaxial surface layer of opposite conductivity type. A semiconductor power device, such as a high-power diode or lateral MOS transistor, is located in the epitaxial layer and forms a p-n junction diode with the substrate. The power integrated circuit also includes a separate semiconductor well region in the epitaxial layer, in which one or more low-power semiconductor circuit elements are formed. In order to minimize the problem of latch up in the low-power circuit elements due to the injection of minority carriers from the substrate, the power integrated circuit is provided with a collector region and an isolation region between the power device and the well region having the low-power circuit elements.

Abstract: In a driver circuit, high- and low-impedance drive means (26 and 28 respectively) operate in parallel to effect a desired output transition. Adaptive control means 32 respond to a threshold value of the output signal (VO) and turn off the low-impedance drive means in the course of the output transition. The low initial output impedance of the driver circuit effects rapid charging of a line capacitance CL, while toward the end of the output transition the higher output impedance of the driver circuit more closely matches the input impedance ZL of a load circuit. This higher impedance dampens ringing and thereby reduces induced supply line noise which is conventionally associated with high-speed driver circuits.

Abstract: Parallel heat paths are provided by three nested tubes, the outer tube being of stainless steel and connected cantilevered to a housing at ambient temperature. The innermost tube forms a cold finger having a negligible temperature gradient and secured in thermal conductive isolation concentrically within an intermediate cold sleeve tube which is also concentric within the outer tube, the cold finger and cold sleeve tubes being made of copper. The tubes have a minimum diameter and specular facing surfaces to minimize radiation coupling which is the major source of heat transfer between the tubes. The two inner tubes have minimum thermal conductive coupling via thermal insulating tapered rings at one end and a thermal insulating support at the other end. A radiation detector is secured to the inner cold finger tube for receiving X-ray radiation from a specimen in an electron microscope. The other ends of the two inner tubes ar thermally conductively connected to a heat sink Dewar via braided copper straps.

Abstract: A nonvolatile trench memory device such as an EEPROM is made by a method which permits an extremely compact and simple configuration due to the use of precise and efficient self-alignment techniques. Oxide-capped polysilicon mesas, formed integrally with the control gates, form the word lines of the memory device, while drain metallization lines contact drain regions of the device and extend over the oxide-capped word lines to form the bit lines. The resulting device is extremely compact, since the self-aligned process permits tighter tolerances and the unique polysilicon mesa/oxide cap construction permits a more compact configuration.

Abstract: A lateral trench-gate bipolar transistor device includes spaced-apart, surface-adjoining, laterally-oriented anode and cathode regions. A channel region at least partially surrounds the cathode region, and a gate region is provided adjacent to, but insulated from, the cathode region and the channel region. The gate region extends in a substantially vertical direction adjacent the cathode region and the channel region in order to induce a substantially vertical conduction channel in the channel region of the lateral device during operation. The gate region can advantageously be provided in a trench surrounding the transistor device, with a trench-shaped gate dielectric layer being provided on the trench sidewalls and floor to insulate the gate from the remainder of the device. Devices may be fabricated in an epitaxial surface layer, which may be provided either directly on a semiconductor substrate, or else on an intervening insulating layer.

Abstract: A fluorescent lamp lighting arrangement controlled by both a motion detector and a light sensing detector operable when said motion detector senses motion.

Abstract: Maneuvers of a controlled vehicle, such as a car, traveling at moderate to high speeds are planned by propagating cost waves in a configuration space using two search strategies referred to as budding and differential budding. Control is achieved by monitoring properties of the controlled vehicle and adjusting control parameters to achieve motion relative to a frame of reference. The frame of reference may change before the transformation to configuration space occurs. The method transforms goals, obstacles, and the position of the controlled vehicle in task space to a configuration space based on the position of these objects relative to a moving frame of reference. The method also determines a local neighborhood of possible motions based on the control capabilities of the vehicle. In one embodiment, the controlled parameters are time derivatives of the monitored properties. A variation of the method provides for the parallel computation of the configuration space.

Abstract: A process for fabricating a compact bipolar transistor structure is disclosed which eliminates the need for a field oxide isolation region between the collector contact region and emitter of the transistor. An island of non-monocrystalline silicon is formed on top of the transistor structure partially covering the base and collector contact regions. Ribbons of non-insulating material are formed along the sidewalls of the island. The ribbon over the base region is employed to form a narrow emitter region with an annealing step that drives dopant from the ribbon or island into the portion of the base region below the ribbon. An insulating layer is disposed between the transistor structure and the island and ribbon over the collector contact region to insulate the emitter from the collector. Insulating sidewall spacers are formed next to the sidewall ribbons to insulate silicide regions grown over the base region, island and collector contact region for the three transistor contacts.

Abstract: A method of forming isolation trenches in CMOS integrated circuits is disclosed. The trench side walls are covered by a thin oxide layer, and the trenches are filled with a highly doped polysilicon. The doped polysilicon has a high work function which prevents oxide charges from inverting the trench side walls and thereby turns off the parasitic transistors at these side walls to reduce latchup.

Abstract: A compandor system is provided that uses integrated circuitry in combination with fully external controlling devices for unity gain level adjustment without affecting the dynamic range. In addition, the system's stability is maintained. The external control is provided, for instance, by replaceable discrete resistors.

Abstract: A semiconductor device contains a stress-relief layer (46) having a glass transition temperature below 150.degree. C. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer is preferably made by lithographic patterning.

Abstract: A circuit employable as a differential multiplexer (10, 310, or 610) or as a differential logic gate (110, 210, 250, 410, or 510) of either the OR/NOR or EXCLUSIVE OR/EXCLUSIVE NOR type contains four pass gates that operate on four circuit input signals and are controlled by two additional circuit input signals. Two of the pass gates drive a bipolar transistor serially coupled to a first FET driven from the other two pass gates. Likewise, the second pair of pass gates drive another bipolar transistor serially coupled to another FET driven from the first pair of pass gates. The bipolar transistors supply respective circuit output signals. The two FETs are of a first polarity. The circuit preferably includes a pair of FETs of a second polarity opposite to the first polarity. The second pair of FETs are arranged so as to provide output pull-up/pull-down assistance for the bipolar transistors.

Abstract: In power integrated circuits having both control circuit components and at least one power device, the circuit components are typically isolated from the power device by placing them in separate "wells" of opposite conductivity type to that of the underlying substrate. However, when these power integrated circuits are used in applications (such as automotive electronics) where supply voltage can be inadvertently reversed, large and potentially damaging currents can flow through the circuit components. In order to prevent such large reverse currents from flowing, an additional p-n junction is incorporated within the circuit "well", thus preventing undesirably large reverse current flow. However, introduction of this addition p-n junction creates a vertical transistor within the device, thus creating another potentially damaging current path and also creating potential reverse breakdown voltage problems.

Abstract: An Erasable and Programmable Read Only Memory (EEPROM) cell is provided with an insulated control gate and an insulating floating gate formed in a trench in a semiconductor body. A surface-adjoining drain region is provided alongside an upper portion of a sidewall of the trench, while a source region is provided alongside a lower portion of the trench sidewall, with a channel region extending along the sidewall of the trench between the source and drain regions. The EEPROM cell is programmed by hot electron injection through the sidewall of the trench alongside the channel region, and is erased by Fowler Nordhiem tunneling through a corner region in the bottom of the trench by creating a localized high electric field density in the corner region. In this manner, a highly compact, efficient and durable EEPROM cell is obtained.

Abstract: The driver circuit comprises drive means (Q2) for drawing an output current from a bus line (13) in a first state of the circuit. An output diode (S1) in the path of the output current is reverse biased in a second state of the circuit to isolate the drive means from the bus line. A control current (I.sub.Q2B) for the drive transistor is drawn from the bus line (13), beyond the output diode (S1). By this means, power dissipation (heat) within the driver circuit due to the control current is eliminated. The driver circuit also comprises means (26, S3, P1) for biasing the output during connection of the circuit to a live bus line, so as to reduce noise for other circuits connected to the bus line.

Abstract: An input/output (I/O) processor and data processing system in which the processor receives and services interrupt request signals from I/O controllers, which requests may be internally or externally coded, and supervises blockwise transfer of data between an external memory associated with a main processing unit and the I/O controllers. The I/O processor includes an internal memory for storing information pertinent to data transfer from each I/O channel including the address where channel programs, decision tables and data buffers are maintained in external memory. A sequencer executes a specialized instruction set which includes instructions that invoke an interpretation means enabling examination of status registers of the I/O controllers and/or data values therefrom and the branching of execution based thereon.

Abstract: A Multiple Instruction Stream Multiple Data Stream (MIMD) parallel processing apparatus and compiling method for effectuating collective branching of execution by the processors includes specialized branch and fuzzy barrier units which operate with respect to special instructions scheduled in unshaded regions of the instruction streams of the processors involved in a collective branch. A special compare instruction is scheduled in a first unshaded region of only one of the processors while a special jump instruction is scheduled in the next unshaded region of the instruction stream of the other involved processors. By the special jump instruction, the other processors use the special compare result which is simultaneously passed to each of them by the branch unit for determining the execution branch. The barrier unit provides fuzzy barrier synchronization assuring that the correct compare result is used in this determination.