Abstract: A sensing system for sensing acoustic waves, the sensing system comprises one or more sensor elements for use underwater, a reference sensor, and compensation means for compensating noise generated in the sensing system in dependence upon signals provided by the sensor elements and the reference sensor.

Abstract: A transistor memory cell device comprising a pair of cross-coupled transistors constituting storage elements for storing binary information and having column drive emitter inputs to which a relatively high column drive current is applied for the selective read or write operation of storage elements of the cell device. A constant current source provides a relatively low value hold current to maintain the binary digit information stored in the storage elements in the absence of column drive current. A voltage clamping dual emitter transistor has the emitters thereof connected directly to the respective base-collector interconnections of the cross-coupled transistors, with the base of the clamping transistor having applied to it an offset voltage higher than a voltage applied to a non select line connected to the collector circuits of the cross-coupled transistors.

Abstract: A method of controlling the flow of gas emerging from the outlet of a fluidic vortex valve, the method comprising feeding a supply fluid to an inlet of the vortex chamber associated with the fluidic vortex valve whereby a supply gas flow is injected into the vortex chamber in a substantially radial direction, feeding in a controlled manner via a valve member a control fluid to a second inlet of the vortex chamber whereby a control fluid flow is injected into the vortex chamber in a substantially tangential direction wherein the improvement lies in providing that the control fluid is in the form of a liquid monopropellant at least until after it has flowed past the valve member, and providing means for igniting the liquid monopropellant thereafter to generate the control gas flow in the vortex chamber.

Abstract: An optical switch array comprises a plurality of optical switches of the kind utilizing the interaction between light propagating along one of two waveguide path sections in close proximity to one another and an electrical field produced by electric switching voltages applied between electrodes actively associated with the waveguide path sections in order to effect switching of the light from one of the waveguide path sections to the other. The waveguide path sections which provide links between the optical switches of the array and which require electrical isolation from one another have dissimilar physical or other characteristics in order to prevent coupling therebetween in the presence of a nearby electric field.

Abstract: The invention provides switching arrangments for use in digital telecommunications exchange systems for local subscriber access and comprises a selector means (PUBS) which is arranged to interface between a plurality of time division multiplex highway groups (G0 to G3) and a plurality of channel digital traffic paths (C0 to C5). The selector means (PUBS) is microprocessor controlled (MCI) to effect a plurality of different switching connectivity modes enabling bothway communication between various combinations of the time division multiplex highway groups and the channel traffic paths when the input and output data rates (1 Mbit/sec, 64 Mbit/sec or 32 Mbit/sec) of the particular connectivity mode is either compatible or incompatible.

Abstract: The subscriber line interface modem is for use in a telecommunications system line interface module which also includes subscriber signalling and switching circuits and a control microprocessor. The modem comprises bus interfacing means, channel means and clock supply means. The interfacing means receives address data and control information from the microprocessor and dispatches address, data and control information to the microprocessor for evaluation. The channel means includes a non-return to zero/conditioned diphase modulation (NRZ/CDM) conversion means which receives NRZ coded information from the circuits and dispatches CDM information to the subscriber line. A CDM/NRZ conversion means receives CDM information from the subscriber line and dispatches NRZ coded information to the circuits. The processing of information through the modem is controlled by the microprocessor in conjunction with the clock signals generated by the clock supply means.

Abstract: An oscillator of balanced design in which a resonant impedance network is connected between the control ports of two matched transistors, and a capacitance is connected in parallel, across the two inputs of these transistors. The inputs of the transistors are connected each to a matched current source. The signals at the transistor outputs are summed together at a common node. Signals of resonant frequency in each arm of the oscillator are equal in magnitude but opposite in phase. Signals at resonant frequency thus cancel whereas signals at the second harmonic frequency add constructively and are thus enhanced. The effect is a net frequency doubling. For high frequency operation, bipolar transistors are utilized. The current sources can be modulated and an IF mixer output derived. Signal of resonant frequency can be extracted and used for signal prescaling. In an equivalent arrangement, an inductance and resonant network replace the resonant network and capacitance just mentioned.

Abstract: A lock detect circuit (FIG. 3) for use in a synthesiser of the type comprising a phase comparator (5), a reference frequency source (11, 13, 15) a variable frequency oscillator (1), a variable divider (3) and a loop amplifier (7). The circuit includes logic gates (31, 33, . . . 41) to monitor the frequency `up` and frequency `down` error signals (C.sub.U, C.sub.D) produced by the comparator (5) and provides an `in-lock` indication (S) when frequency `up` or frequency `down` signals exclusively are detected in a predetermined period ( .sub.D). Accordingly this circuit may comprise a variable delay (31) an inverter (33) an AND-gate (35) and an OR-gate (39) for generating a comparison signal:f'.sub.E =F.sub.N .multidot.C.sub.D +C.sub.Uwhere f.sub.N is the signal from the inverter time delay pair derived from the divider output. This signal is fed to a series of flip-flops (37) clocked by the frequency down signal.

Abstract: A frequency dividing arrangement comprises an injection-locked divider arranged for receiving an incoming signal F.sub.in and for providing a frequency divided signal F.sub.out in response thereto, and a frequency divider coupled to the injection-locked divider. The frequency divider comprises logical circuits for providing a further frequency divided signalF".sub.out in response to the frequency divided signal F.sub.out provided by the injection-locked divider. The arrangement may be included in a frequency modulation receiver which comprises an FM detector. The injection-locked divider comprises a multiplier, and a tuning circuit.

Abstract: A circuit comprising three stages, a differential input stage, a store and integrate stage, and a differential output stage. Both input and output stages are co-operative with enable/disable switching, which switching is controlled by timing signals provided externally to control the periods of integration and data reading. The store and integrate stage comprises a pair of transistors and individual current sources, charge being integrated by a capacitor connected between the transistors. At the end of each period of integration the capacitor may be discharged via these sources, or, parallel sources and a further switch may be added to allow separate reset and hole period provision. Such circuits may be combined and timed out in phased sequence for fastest operation. They may be incorporated in Costas phase-locked loops and used as a means of communication data recovery.

Abstract: A frequency synthesizer of the fractional N type comprising a voltage controlled oscillator for producing an output signal which is afforded to a phase detector via a variable divider to provide a control signal for the voltage controlled oscillator in the presence of a phase difference between a reference signal from a reference source and the signal afforded thereto from the variable divider wherein the division ratio of the variable divider is set in dependence upon the output of an interpolator arrangement comprising combiner means for receiving a digital input, digital controller means for receiving an output from the combiner means, digital slicer means for receiving an output from the digital controller means, feedback means for affording the output of the digital slicer means to a component for varying the division ratio of the variable divider.

Abstract: A method of producing a heterostructure device comprises defining in a substrate 5 of group III-V semiconductor material a structure, such as a mesa 9, having first and second faces oriented substantially parallel to the (100) and (111)A crystallographic planes. The mesa 9 is exposed to group III-V chemical reagents thereby to deposit group III-V materials on the first and/or second faces in dependence upon the group V constituent in the chemical reagents.

Abstract: An electrical detector arrangement is provided having a chopper device for alternately exposing to and obscuring from a detector array a thermal radiation pattern to be detected and imaged. The outputs from the detectors of the array are multiplexed by a multiplexer and then digitized by means of a low cost analogue-to-digital converter. The digital output from the coverter during obscuration of the detector array from the thermal radiation pattern is stored in memory means and this stored data is converted to an analogue signal by a digital-to-analogue converter subtracted from the output of the multiplexer during exposure to and obscuration from the thermal pattern of the detector array by means of a differential amplifier. The output from the differential amplifier which substantially reduces the offset level of the multiplexed detector outputs is then fed to a further low cost analogue-to-digital converter.

Abstract: An optical device comprising a length of optical fibre of predetermined convex configuration supported by fibre mounting and/or attachment means, the convex outer part of the optical fibre having a portion thereof removed therefrom closely adjacent to or even just entering the core of the optical fibre to produce a substantially flat surface therealong on which a reflective diffraction grating of predetermined form is provided according to the function requirements of the device.

Abstract: In a tuner circuit, the relatively high voltage used to control a varactor diode of the circuit is derived using a cascade of resistors and transistors under the control of a reference voltage input. The breakdown voltage of each transistor is significantly less than the output voltage of the cascade and is such that the cascade can be implimented in the same semiconductor chip as high frequency, low voltage process, synthesiser components.

Abstract: A linear A to D converter comprising a combiner means to which an input signal to be converted is fed, the input signal being combined subtractively or additively with an analogue feedback signal, and the combiner means being arranged to feed an A to D flash converter via an amplifier, which A to D flash converter is arranged to feed a D to A converter which provides the feedback signal. The D to A converter comprises a digital overflowing accumulator also arranged to drive a finite impulse response filter having a plurality of serially coupled one bit delay elements, output signals from which are summed to provide the digital output signal.

Abstract: A coupler (FIG. 4) comprising a pair of interwined monomode fibers optically coupled along a portion of their length. The diameter of one fiber is significantly smaller than that of the other and this fiber is thus wound helically. A helical pitch not exceeding 10 mm is chosen. For such pitch, the smaller diameter fiber is appreciably longer. The following inequality thus holds:.lambda..sub.c .multidot.L/.DELTA.L.ltoreq.L.sub.c :where.lambda..sub.c is the design wavelength,.DELTA.L/L is the difference in fiber lengths per unit length, and L.sub.c is the interaction length of the coupler. The signal coupling of the coupler is than a strongly peaked function of wavelength. The coupler is suited to wavelength multiplex/demultiplex applications.