Patents Assigned to Powerchip Semiconductor Manufacturing Corporation
  • Patent number: 11513880
    Abstract: A failure bit count (FBC) circuit for memory array is provided. The memory array includes pages each having plural sectors and a redundancy column. The FBC circuit includes FBC units, in which each FBC unit is respectively coupled to each sector for providing a failure bit count current; a redundancy FBC unit coupled to the redundancy column and provides a redundancy current; a switch having a first end and a second end capable of being switched to couple to one of outputs of the FBC units to receive the failure bit count current from one of the FBC units; a comparator having a first input end that receives a reference current, and a second input end that receives a measurement current obtained by adding the failure measurement current and the redundancy current, and an output end outputting a judge signal to indicate a number of failure bits for each sector.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: November 29, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Tomofumi Kitani
  • Patent number: 11508739
    Abstract: A method of manufacturing a memory structure including the following steps is provided. A first pad layer is formed on a substrate. Isolation structures are formed in the first pad layer and the substrate. At least one shape modification treatment is performed on the isolation structures. Each shape modification treatment includes the following steps. A first etching process is performed on the first pad layer to reduce a height of the first pad layer and to form first openings exposing sidewalls of the isolation structures. After the first etching process is performed, a second etching process is performed on the isolation structures to modify shapes of the sidewalls of the isolation structures exposed by the first openings. The first pad layer is removed to form a second opening between two adjacent isolation structures.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: November 22, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Hui-Chin Huang, Kai-Yao Shih, Yu-Mei Liao, Hsin-Yi Liao
  • Publication number: 20220366963
    Abstract: A flash memory storage apparatus includes a memory cell array and a voltage generating circuit. The memory cell array includes at least one memory cell string coupled between a bit line and a source line and including memory cells; each memory cell is coupled to a corresponding word line. The voltage generating circuit is coupled to the memory cell array and configured to output a bias voltage to the word line. A first voltage is applied to a selected word line. A second voltage and a third voltage are applied to unselected second and third word lines, respectively. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage. The second word line and the third word line are located on two sides of the first word line. A biasing method of a flash memory storage apparatus is also provided.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chien-Hung Lien, Chih-Yuan Wang
  • Patent number: 11496119
    Abstract: An oscillator circuit is provided. A first and a second cycle generating units, and a first and a second duty generating units are included. An SR latch, receiving outputs the first and second cycle generating units. In the SR latch, an output is provided to the first cycle generating unit and the third duty generating, and a contemporary output is provided to the second cycle generating unit and the second duty generating unit. A logic circuit receives the outputs of the first and the second duty generating units and the output and the contemporary output of the SR latch to generate a clock signal. The first and the second cycle generating units are respectively operated to provide the even and odd cycle times of the clock signal. The first and the second duty generating units are respectively operated to provide the even and odd duties of the clock signal.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: November 8, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Tomofumi Kitani
  • Patent number: 11488965
    Abstract: An SRAM memory device includes a substrate, a first transistor, a second transistor, a metal interconnect structure, and a capacitor. The metal interconnect structure is formed on the first and second transistors. The capacitor is disposed in the metal interconnect structure and coupled between the first transistor and the second transistor. The capacitor includes a lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The lower metal layer is coupled to a source node of the first transistor and a source node of the second transistor. The lower metal layer and an n-th metal layer in the metal interconnect structure are formed of a same material, wherein n?1; the upper metal layer and an m-th metal layer in the metal interconnect structure are formed of a same material, wherein m?n+1.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: November 1, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Yi-Hsung Wei, Pei-Hsiu Tseng, Jia-You Lin
  • Publication number: 20220344398
    Abstract: A method of fabricating a solid-state image sensor, including steps of forming a second type doped semiconductor layer and a semiconductor material layer sequentially on a first type doped semiconductor substrate to constitute a photoelectric conversion portion, forming a multilayer structure on the semiconductor material layer, wherein a refractive index of the multilayer structure gradually decreases from a bottom layer to a top layer of the multilayer structure and is smaller than a refractive index of the semiconductor material layer, and performing a photolithography process to the multiplayer structure and the photoelectric conversion portion to form multiple micro pillars, wherein the micro pillars protrude from the semiconductor material layer and are isolated by recesses extending into the photoelectric conversion portion.
    Type: Application
    Filed: July 10, 2022
    Publication date: October 27, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Yi-Ping Lin, Yu-Ching Liao, Ya-Ting Chen, Hsin-Ying Tung
  • Publication number: 20220336621
    Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wen Chung Yang, Shih Hsi Chen, Wei-Chang Lin
  • Patent number: 11475963
    Abstract: A semiconductor memory and a data protection method are provided. The semiconductor memory includes a memory array, a switch circuit, a control circuit and a power-down monitor circuit. The switch circuit is coupled to the memory array. The control circuit is coupled to the switch circuit. The power-down monitor circuit is coupled to the control circuit and a supply voltage. The power-down monitor circuit is configured to determine whether that the supply voltage drops below a first power-down detect level during a programming period, to output a trigger signal to the control circuit. The control circuit executes a reset sequence of the semiconductor memory according to the trigger signal. The first power-down detect level is lower than a minimum value of the supply voltage recorded in a datasheet of the semiconductor memory.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: October 18, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Munehiro Yoshida
  • Publication number: 20220320341
    Abstract: A method for manufacturing a non-volatile memory device includes forming a device isolation structure in a substrate, forming a floating gate, an inner layer dielectric (ILD) layer, and a floating gate contact on the substrate, and forming an interconnect structure on the ILD layer. The interconnect structure includes alternately stacked metal layers and inter metal dielectric (IMD) layers and vias connecting the upper and lower metal layers. In the method, after the ILD layer is formed, first and second comb-shaped contacts are simultaneously formed in at least one of the ILD layer and the IMD layers above the device isolation structure, wherein the first comb-shaped contact s a floating gate extension part, and the second comb-shaped contact is a control gate. During the forming of the interconnect structure, a structure is simultaneously formed for electrically connecting the floating gate extension part to the floating gate contact.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shiangshiou Yen, Bo-An Tsai
  • Publication number: 20220310780
    Abstract: A semiconductor device including a substrate and a capacitor is provided. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The first electrode has a plurality of hemispherical recesses. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode. Surfaces of the hemispherical recesses are in direct contact with the insulating layer.
    Type: Application
    Filed: May 5, 2021
    Publication date: September 29, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ching-Sung Ho, Jia-Horng Tsai
  • Publication number: 20220310781
    Abstract: A method of manufacturing a capacitor structure of memory, including forming a patterned photoresist layer on a hard mask layer and spacers on sidewalls of the patterned photoresist layer, perform a first etch process to remove uncovered hard mask layer so as to form first patterned hard mask layer and expose first portion of the dielectric layer, lowering a surface of the first portion of dielectric layer, perform a second etch process to remove uncovered first patterned hard mask layer so as to form second patterned hard mask layer and expose second portion of the dielectric layer, and performing a hole etching process to form first holes and second holes respectively in the first portion and the second portion of dielectric layer, wherein sidewalls of the first holes and second holes have wavelike cross-sections, and the wavelike cross-sections of first holes and second holes are shifted vertically by a distance.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Kai-Jyun Huang
  • Publication number: 20220310564
    Abstract: A circuit structure for testing through silicon vias (TSVs) in a 3D IC, including a TSV area with multiple TSVs formed therein, and a switch circuit with multiple column lines and row lines forming an addressable test array, wherein two ends of each TSV are connected respectively with a column line and a row line. The switch circuit applies test voltage signals through one of the row lines to the TSVs in the same row and receives current signals flowing through the TSVs in the row from the columns lines, or the switch circuit applies test voltage signals through one of the column lines to the TSVs in the same column and receives current signals flowing through the TSVs in the column from the row lines.
    Type: Application
    Filed: July 13, 2021
    Publication date: September 29, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shou-Zen Chang, Chun-Lin Lu, Chun-Cheng Chen
  • Publication number: 20220301641
    Abstract: A semiconductor memory and a data protection method are provided. The semiconductor memory includes a memory array, a switch circuit, a control circuit and a power-down monitor circuit. The switch circuit is coupled to the memory array. The control circuit is coupled to the switch circuit. The power-down monitor circuit is coupled to the control circuit and a supply voltage. The power-down monitor circuit is configured to determine whether that the supply voltage drops below a first power-down detect level during a programming period, to output a trigger signal to the control circuit. The control circuit executes a reset sequence of the semiconductor memory according to the trigger signal. The first power-down detect level is lower than a minimum value of the supply voltage recorded in a datasheet of the semiconductor memory.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Munehiro Yoshida
  • Publication number: 20220302082
    Abstract: A semiconductor package including a chip stack structure, a redistribution layer (RDL) structure and conductive plugs is provided. The chip stack structure includes stacked chips. Each of the chips includes a pad. The pads on the chips are located on the same side of the chip stack structure. The RDL structure is disposed on the first sidewall of the chip stack structure and adjacent to the pads. The conductive plugs penetrate through the RDL structure. The conductive plug is connected to the corresponding pad.
    Type: Application
    Filed: May 13, 2021
    Publication date: September 22, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang
  • Patent number: 11449983
    Abstract: A defect identification method and an image analysis system are provided. The defect identification method includes the following steps: adjusting a gray level distribution of a first image corresponding to a reference image of a defect on a wafer to generate a second image; capturing a defect of interest image in the second image; analyzing a plurality of pixels of the defect of interest image to obtain a minimum gray level value of the pixels; analyzing the pixels of the second image according to the minimum gray level value, so as to obtain a number of defect of interest pixels and a number of non-defect of interest pixels; dividing the number of defect of interest pixels by the number of non-defect of interest pixels to obtain a proportional value; and determining a defect type of the defect in the first image according to the proportional value.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: September 20, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yue-Ying Yen
  • Patent number: 11450355
    Abstract: A semiconductor memory with temperature dependence is provided. The semiconductor memory includes a memory array, a temperature sensor circuit and a pump circuit. The temperature sensor circuit is configured to provide a temperature dependent signal. The pump circuit is coupled to the temperature sensor circuit and the memory array. The pump circuit is configured to output a charge-pump output voltage to the memory array according to the temperature dependent signal. The charge-pump output voltage depends on the temperature dependent signal.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: September 20, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Jun Setogawa
  • Patent number: 11450402
    Abstract: A sensing circuit is provided which generates a sensing result according to a reading voltage of a non-volatile memory. The sensing circuit includes four transistors and a switch group. A first transistor is coupled between an operating voltage and a first node. A second transistor is coupled between the first node and a second node. A third transistor is coupled between the second node and a reference ground voltage. A control terminal of the first transistor, a control terminal of the second transistor, and a control terminal of the third transistor all receive the reading voltage. A fourth transistor is coupled between the operating voltage and the first node. The switch group forms or disconnects a conduction path between a control terminal of the fourth transistor and the second node according to a control signal, so that the first node obtains the sensing result.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: September 20, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chien-Fa Lee, Yi-Chun Lin
  • Publication number: 20220293585
    Abstract: A silicon-controlled rectifier includes a substrate of a first conductivity type; a deep well region of a second conductivity type; a well regions of the first conductivity type and the second conductivity type; a first, second and third heavily doped active regions of the first conductivity type; a first, second and third heavily doped active regions of the second conductivity type; and a first, second and third shallow trench isolation structures. A reverse diode formed in the third heavily doped active region of the second conductivity type and the well region of the first conductivity type is embedded, and a forward diode is formed in the heavily doped active region of the first conductivity type and the well region of the second conductivity type. By sharing the third heavily doped active region of the second conductivity type across the well regions of different conductivity types, two back-to-back diodes are formed.
    Type: Application
    Filed: March 31, 2021
    Publication date: September 15, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Juin Jei Liou, Wenqiang Song, Ching-Sung Ho
  • Patent number: 11443185
    Abstract: A memory chip capable of performing artificial intelligence operation and an operation method thereof are provided. The memory chip includes a memory array, a memory controller, and an artificial intelligence engine. The memory array includes a plurality of memory areas. The memory areas are configured to store digitized input data and weight data. The memory controller is coupled to the memory array via a bus dedicated to the artificial intelligence engine. The artificial intelligence engine accesses the memory array via the memory controller and the bus to obtain the digitized input data and the weight data. The artificial intelligence engine performs a neural network operation based on the digitized input data and the weight data.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 13, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Frank Chong-Jen Huang, Yung-Nien Koh
  • Publication number: 20220284966
    Abstract: A static random access memory including at least one memory cell is provided. The memory cell includes a first inverter, a second inverter, a first pass gate transistor, a second pass gate transistor, a first non-volatile memory, and a second non-volatile memory. The first inverter and the second inverter are coupled to each other. The first pass gate transistor is coupled between the first inverter and the first bit line. The second pass gate transistor is coupled between the second inverter and the second bit line. The first non-volatile memory is coupled between the first pass gate transistor and the first bit line. The second non-volatile memory is coupled between the second pass gate transistor and the second bit line.
    Type: Application
    Filed: April 13, 2021
    Publication date: September 8, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang