Abstract: An integrated circuit includes a first electrode including an inner portion and an outer portion laterally surrounding the inner portion. The outer portion has a greater resistivity than the inner portion. The integrated circuit includes a second electrode and resistivity changing material contacting the first electrode and coupled to the second electrode.

Abstract: A voltage regulator comprises first and second amplifier stages, a common-source output stage and a feedback path. The output stage drives a capacitive load with a regulated voltage responsive to a signal applied to the output stage. The capacitive load sets the dominant pole of the voltage regulator. The first amplifier stage amplifies the difference between the regulated voltage and a reference voltage. The second amplifier stage drives the output stage with a signal corresponding to the difference between the regulated voltage and the reference voltage. The feedback path couples an output node of the second amplifier stage to an input node of the second amplifier stage for reducing the output resistance of the second amplifier stage to shift a non-dominant pole of the voltage regulator set by the second amplifier stage.

Abstract: In one embodiment, a memory device comprises a plurality of banks and a refresh controller. Each bank is logically divisible into at least two different sections of memory cells during a refresh operation. The refresh controller successively identifies each of the sections using a first portion of a row address and addresses a row of memory cells included in each of the sections using a second portion of the row address. The refresh controller also successively selects two or more different groups of the banks during different time intervals each time a different one of the sections is identified. The refresh controller refreshes the addressed row of memory cells included in the most recently identified section of each bank for the most recently selected group of banks.

Abstract: Embodiments of the invention are generally related to systems comprising devices connected by a bus. A device in the system may include termination control logic capable of detecting changes in the system clock frequency. Upon detecting a clock frequency, the termination control logic may determine whether the clock frequency is greater than a threshold frequency. If so, the termination control logic may enable bus termination. However, if the new clock frequency is lower than the threshold frequency, bus termination may be disabled, thereby conserving power.

Abstract: An integrated circuit includes a vertical diode defined by crossed line lithography.

Abstract: One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and store the locked state data. The control circuit is configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period. The control circuit controls the length of the update interval and the length of the enable period to adjust lock state acquisition time for the delay locked loop in exiting the standby mode.

Abstract: A voltage regulator circuit is operated by enabling a bias network operable to set a bias current in an amplifier. A startup circuit is connected to the bias network, the startup circuit operable to assist the bias network in setting the amplifier bias current during a startup period. The startup circuit is disconnected from the bias network responsive to the startup period lapsing while the voltage regulator circuit is enabled for resetting the startup circuit to an initial state. The bias network may be disabled to reduce the amplifier bias current. Subsequent re-enablement of the bias network is prevented until the amplifier is reliably disabled.

Abstract: Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.

Abstract: An integrated circuit includes a first electrode, a second electrode, and dielectric material including an opening. The opening is defined by etching the dielectric material based on an oxidized polysilicon mask formed using a keyhole process. The integrated circuit includes resistivity changing material deposited in the opening and coupled between the first electrode and the second electrode.

Abstract: An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode and the second electrode. The first resistivity changing material and the second resistivity changing material have different crystallization speeds.

Abstract: In one embodiment, an electronic device comprises control circuitry. The control circuitry disables termination circuitry coupled to one or more input/output (I/O) signals of the electronic device during at least a portion of a relatively low frequency operation which causes insubstantial signal reflections at the I/O signals. The control circuitry re-enables the termination circuitry prior to the electronic device performing a relatively high frequency operation after completion of the low frequency operation, the high frequency operation causing substantial signal reflections at the I/O signals. The electronic device is a memory device in one embodiment. This way, the termination circuitry may be disabled during at least a portion of a refresh operation performed by the memory device and re-enabled prior to the memory device resuming normal operation (i.e., reads and writes) after completion of the refresh operation.

Abstract: A memory includes an array of resistive memory cells, bit lines between rows of the memory cells for accessing the memory cells, and a conductive plate coupled to each of the memory cells.

Abstract: Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are compared to device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

Abstract: An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test.

Abstract: A memory includes a first multi-bit resistive memory cell and a single bit resistive memory cell. The single bit resistive memory cell is for storing a bit indicating whether data stored in the first multi-bit resistive memory cell is inverted.

Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.

Abstract: In one embodiment, a memory device comprises a plurality of banks and a refresh controller. Each bank is logically divisible into at least two different sections of memory cells during a refresh operation. The refresh controller successively identifies each of the sections using a first portion of a row address and addresses a row of memory cells included in each of the sections using a second portion of the row address. The refresh controller also successively selects two or more different groups of the banks during different time intervals each time a different one of the sections is identified. The refresh controller refreshes the addressed row of memory cells included in the most recently identified section of each bank for the most recently selected group of banks.

Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.

Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material between the first electrode and the second electrode. The phase-change material has a step-like programming characteristic.

Abstract: A memory device includes sense amplifier circuitry, a current sink and a resistive element. The sense amplifier circuitry is operable to evaluate data read from a memory array included in the memory device responsive to a bias voltage applied to the sense amplifier circuitry. The current sink is operable to sink a bias current. The resistive element couples the current sink to the sense amplifier circuitry. The bias voltage applied to the sense amplifier circuitry corresponds to the voltage drop across the resistive element and current sink as induced by the bias current.