Abstract: An integrated circuit includes an array of resistive memory cells having varying critical dimensions and a write circuit. The write circuit is configured to reset a selected memory cell by applying a first pulse having a first amplitude and a second pulse having a second amplitude less than the first amplitude to the selected memory cell.

Abstract: A memory includes an input pad for receiving an input signal and a first circuit. The first circuit is configured to receive a first signal in response to the input signal and receive a second signal and provide a third signal in response to at least one of the first signal and the second signal indicating a request to enter a deep power down mode. The memory includes a second circuit configured to provide a fourth signal indicating an entry to the deep power down mode in response to the third signal.

Abstract: An integrated circuit includes a memory element and a circuit. The circuit is configured to program the memory element by applying one or more pulses to the memory element until a sensed resistance of the memory element is within a range of a desired resistance. The one or more pulses have a parameter value that is modified for each subsequent pulse based on the parameter value for an immediately preceding pulse and on a difference between the sensed resistance of the memory element and the desired resistance.

Abstract: A sense amplifier enable signal generator has two stages. Each stage offsets transistor performance variation in the other stage to produce an enable signal output relatively immune from the effects associated with transistor mismatches. In one embodiment, a memory device comprises a plurality of memory cells, sense amplifier circuitry and the enable signal generator. The sense amplifier circuitry is coupled to one or more of the memory cells and senses the state of the one or more memory cells when enabled. The enable signal generator has first and second stages and generates an enable signal applied to the sense amplifier circuitry. The enable signal generator counteracts delay variation when generating the enable signal so that operation of the enable signal generator is substantially unaffected by transistor performance variation in either stage of the enable signal generator.

Abstract: An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming an interface layer, removing a portion of the interface layer, annealing the interface layer, and forming a dielectric material over the interface layer.

Abstract: A redundancy replacement scheme for a semiconductor device repairing a faulty memory cell in a column select line group with a spare memory cell in the column select line group based on a physical or logical address of the selected row.

Abstract: An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows selectable through a row address. The refresh controller is configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.

Abstract: A memory includes a bit line and a plurality of resistive memory cells coupled to the bit line. Each resistive memory cell is programmable to each of at least three resistance states. The memory includes a first resistor for selectively coupling to the bit line to form a first current divider with a selected memory cell during a read operation.

Abstract: An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.

Abstract: Methods and circuits for detecting variations in signal propagation rates within an electronic device, and for adjusting the output timing of the device in response to the variations in signal propagation rates. According to an embodiment of the invention, a signal may be propagated through an uncompensated delay chain and a compensated delay chain. If the signal passes through the compensated chain slower than through the uncompensated delay chain, then the device may delay a clock signal such that the output timing of the device will remain within the specification parameters. In contrast, if the signal passes through the uncompensated delay chain slower than through the compensated delay chain, the device may not delay the received clock signal such that the output timing of the device will remain within specification parameters.

Abstract: An integrated circuit includes a logic portion including M conductive layers, a memory portion including N conductive layers, and at least one common top conductive layer over the logic portion and the memory portion. M is greater than N.

Abstract: An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion and a second portion. The first portion contacts the first electrode and has a same cross-sectional width as the first electrode. The second portion has a greater cross-sectional width than the first portion. The integrated circuit includes a second electrode coupled to the resistivity changing material.

Abstract: A memory cell includes a first electrode and a second electrode forming an opening. The opening is defined by a first sidewall, a second sidewall, and a surface extending between the first sidewall and the second sidewall. The memory cell includes phase change material contacting the first electrode and the first sidewall and the second sidewall. The memory cell includes isolation material electrically isolating the phase change material from the surface extending between the first sidewall and the second sidewall.

Abstract: A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.

Abstract: A memory device includes an array of resistive memory cells, a counter having an increment step based on temperature, and a circuit for refreshing the memory cells in response to the counter exceeding a preset value.

Abstract: Embodiments of the invention generally provide methods, systems, and articles of manufacture for selecting a data bus inversion (DBI) mode of operation. A comparison circuit of a device may receive multiple packets of data to be transmitted to another device over a bus connecting the devices. The comparison circuit may compare the multiple packets of data and select a DBI mode of operation that conserves power and reduces noise on the bus.

Abstract: A memory device includes a first bit line in a first conducting layer and a second bit line parallel to the first bit line. The second bit line is in a second conducting layer. The memory device includes a MOS select transistor and a word line coupled to a gate of the MOS select transistor. The word line is at an angle with respect to the first bit line and the second bit line. The memory device includes a first resistive memory element coupled between a source of the MOS select transistor and the first bit line. The memory device includes a second resistive memory element coupled between a drain of the MOS select transistor and the second bit line.

Abstract: A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.

Abstract: A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.