Abstract: A system on a chip (SoC) includes an on-screen display (OSD) circuit, a memory control circuit, and an audio processor. The OSD circuit is arranged to control OSD of a text message. The memory control circuit is coupled to a memory, and is arranged to read a text-to-speech (TTS) data corresponding to the text message from the memory. The audio processor is coupled to the memory control circuit, and includes a TTS circuit, wherein the TTS circuit is arranged to: receive the TTS data from the memory control circuit, and generate an audio output according to at least the TTS data.

Abstract: A method for resuming topology of a single loop network and a network switch system are provided. The network switch system includes one or more first network switches each having a first port and a second port and a second network switch having a third port and a fourth port. When the first port of one of the first network switches is abnormal, a recovery control frame is transmitted through the second port. The second network switch sets the third port in a disabled state to an enabled state. When the abnormal port is resumed, the first network switch transmits a block control frame through the second port. The second network switch sets the third port in the enabled state to the disabled state and transmits a forward control frame through the fourth port. The first network switch sets the first port in the disabled state to the enabled state.

Abstract: A power capability determination device is arranged to determine a power capability of a power source, and includes a connector, a load circuit, a switch circuit, a voltage monitor circuit, and a processing circuit. The connector is arranged to receive the power source to output an input voltage at a power output terminal. The switch circuit is electrically connected between the load circuit and the power output terminal. The voltage monitor circuit is electrically connected to the power output terminal, and is arranged to monitor the input voltage to generate a monitored voltage value. The processing circuit is electrically connected to the voltage monitor circuit and the switch circuit, and is arranged to control the switch circuit, and in a state of controlling the switch circuit, receive the monitored voltage value and determine the power capability of the power source according to the monitored voltage value.

Abstract: A method for training a deep learning network for face recognition includes: utilizing a face landmark detector to perform face alignment processing on at least one captured image, thereby outputting at least one aligned image; inputting the at least one aligned image to a teacher model to obtain a first output vector; inputting the at least one captured image a student model corresponding to the teacher module to obtain a second output vector; and adjusting parameter settings of the student model according to the first output vector and the second output vector.

Abstract: The present invention provides a receiver including a filter, a signal detection circuit and a synchronization processing circuit. The filter is configured to filter a filter input signal to generate a filter output signal. The signal detection circuit is configured to determine whether the filter input signal or the filter output signal includes an interference signal according to the filter input signal and the filter output signal, to generate an interference signal indicator; wherein when the interference signal indicator indicates that the filter input signal or the filter output signal includes the interference signal, the signal detection circuit further determines whether the filter output signal comprises an effective signal to generate an effective signal indicator. The synchronization processing circuit is configured to process the filter output signal according to the interference signal indicator and the effective signal indicator.

Abstract: The present invention provides a DP-out adapter including a decoder, a clock signal generating circuit, a DP signal generating circuit and a symbol counter value comparator. The decoder is configured to decode a USB signal to generate a plurality of packets. The clock signal generating circuit is configured to generate a clock signal. The DP signal generating circuit is configured to generate a DP signal according to the packets, and output the DP signal according to the clock signal. The symbol counter value comparator is configured to generate a first counter value according to a number of symbols corresponding to the plurality of packets, and use the clock signal to count to obtain a second counter value, and compare the first counter value and the second counter value to generate a control signal to the clock signal generating circuit to adjust a frequency of the clock signal.

Abstract: An embedded electronic device and a boot method are provided. A processor of the embedded electronic device is configured to execute following steps based on a first boot procedure: verifying whether a second memory device safely corresponds to a first memory controller; in response to that the second memory device safely corresponds to the first memory controller, deciphering and verifying stored data of the second memory device through the first memory controller; and in response to that the second memory device does not safely correspond to the first memory controller, verifying whether the second memory device safely corresponds to a second memory controller.

Abstract: A method and an electronic device for processing video coding are provided. The electronic device for processing video coding includes a storage unit, a coding tree generation module, and a decision tree module. The storage unit stores an input video. The input video includes a plurality of frames. The electronic device for processing video performs following steps of: acquiring a target block in each of the frames, where the target block has at least one coding unit; loading the target block to the coding tree generation module to output a first coding tree and a second coding tree; generating an output decision tree according to the first coding tree and the second coding tree; and outputting streaming data according to the output decision tree and the frames.

Abstract: A device includes a first impedance; a reference current generation circuit configured to generate a reference current according to a first potential difference, a reference voltage, and a first impedance value of the first impedance; a current mirror circuit configured to output an output current having a first ratio to the reference current according to the reference current; a second impedance configured to generate an output voltage according to a second impedance value of the second impedance, a voltage of a first node which is the same as the first potential difference, and the output current; and a negative feedback circuit configured to generate a feedback voltage according to the voltage of the first node, and adjust the output voltage according to the feedback voltage. There is a second ratio that is inversely proportional to the first ratio between the second impedance value and the first impedance value.

Abstract: The present invention provides a method for controlling a connection between an ONU and an OLT, wherein the method includes the steps of: (a) downloading an OMCI message from the OLT; (b) enabling an OMCI management program to process the OMCI message to try to generate a plurality of models; (c) if the plurality of models are not successfully generated by using the OMCI management program to process the OMCI message, modifying the OMCI management program to generate a modified OMCI management program when the ONU is not connected with the OLT; and (d) using the modified OMCI management program to process the OMCI message to try to generate the plurality of models.

Abstract: A method used for controlling a wireless communication system includes receiving a packet, demodulating the packet to obtain a first channel characteristic index and a second channel characteristic index of the wireless communication system, selecting a length of a guard interval according to the first channel characteristic index, and selecting a length of a long training field according to the second channel characteristic index. When signal quality corresponding to the packet is higher, the length of the guard interval is shorter, and the length of the long training field is shorter.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.

Abstract: A shielding circuit applied to a semiconductor device includes a first shielding structure and a second shielding structure. The first shielding structure forms a first closed loop and is disposed adjacent to an inductor comprised in the semiconductor device. The second shielding structure forms a second closed loop and is disposed adjacent to an electronic component coupled to the inductor.

Abstract: A hybrid class-D amplifier is provided. The hybrid class-D amplifier includes a digital-to-analog conversion (DAC) input stage circuit, a loop filter circuit electrically coupled to the DAC input stage circuit, a quantizer circuit electrically coupled to the loop filter circuit, an output stage circuit electrically coupled to the quantizer circuit, and a feedback circuit electrically coupled between the output stage circuit and the loop filter circuit. The DAC input stage circuit converts a digital signal into an analog signal. The loop filter circuit generates a filtered signal according to the analog signal and a feedback signal. The quantizer circuit performs a quantization operation on the filtered signal to generate a quantized signal. The output stage circuit performs power amplification on the quantized signal to generate an output signal. The feedback circuit generates the feedback signal according to the output signal.

Abstract: The present invention provides a speed detection circuit positioned in a chip, wherein the speed detection circuit includes a test signal generator, a launch flip-flop, a device under test (DUT), a capture flip-flop, a comparator and a control circuit. The test signal generator is configured to generate a test signal with a specific pattern. The launch flip-flop is configured to use a first clock signal to sample the test signal to generate a sampled test signal. The device under test is configured to receive the sampled test signal to generate a delayed test signal. The capture flip-flop is configured to use a second clock signal to sample the delayed test signal to generate an output signal. The comparator is configured to determine whether the output signal conforms to the specific pattern to generate a comparison result, for the control circuit to determine a speed of the chip.

Abstract: The present invention provides a packet forwarding system including a packet, a packet analyzer and a DMA module. The packet buffer is configured to receive a packet and store the packet. The packet analyzer is configured to read the packet from the packet buffer, and analyze the packet to extract part of content of the packet to generate specific data. The DMA module is configured to write the specific data into a first buffer of a storage device, and write the packet into a second buffer of the storage device.

Abstract: A method for performing media playback on a media playback device includes: generating a quick launch area in a user interface according to a quick launch setting, wherein the quick launch area includes a plurality of windows, and the windows correspond to at least one audio-visual (AV) content and at least one application program respectively; according to the quick launch setting, retrieving data corresponding to the at least one AV content and buffering the data in a first buffering unit; according to the quick launch setting, retrieving data required by executing the at least one application program and buffering the data in a second buffering unit; and in response to a quick launch operation, decoding the data buffered in the first buffering unit to play the AV content, or utilizing the data buffered in the second buffering unit to execute the at least one application program.

Abstract: A display control method includes: receiving a first video signal provided by a first video source device to display one or more first images in the first video signal on a display device; when the display device is displaying the one or more first images, establishing a connection with a second video source device and receiving a second video signal provided by the second video source device through the connection; generating one or more composite images based on the one or more first images in the first video signal and one or more second images in the second video signal without receiving a user control input; and displaying the one or more composite images on the display device.

Abstract: A card reader and a controller thereof, and a method are provided. The card reader includes a storage device and the controller, wherein the controller is coupled to the storage device. The storage device is configured to store specific identification data of a specific memory device. The controller is configured to receive identification data of the external memory device plugged into the card reader, and determine whether the external memory device is the specific memory device according to the identification data and the specific identification data, to generate a determination result. More particularly, the controller may control whether to open permission of at least one function according to the determination result.

Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device, a first Bluetooth member device, and a second Bluetooth member device. The audio broadcasting device broadcasts BLE audio packets and transmits a predetermined volume instruction to the first Bluetooth member device and the second Bluetooth member device before broadcasting the BLE audio packets. The first Bluetooth member device parses the BLE audio packets to acquire a predetermined audio data, controls a first audio playback circuit to playback the predetermined audio data, and configures an audio volume of the first audio playback circuit in advance according to the predetermined volume instruction. The second Bluetooth member device parses the BLE audio packets to acquire the predetermined audio data, controls a second audio playback circuit to playback the predetermined audio data, and configures an audio volume of the second audio playback circuit in advance according to the predetermined volume instruction.