Abstract: An inductor device includes a first trace, a second trace, and a capacitor. The first trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a first node. The second trace includes at least two sub-traces. One terminal of each of the at least two sub-traces are coupled to each other at a second node. The capacitor is coupled to the firs node and the second node.

Abstract: A blind scan method includes setting a tuner to scan a first spectrum block with a first center frequency as a center and determining whether the first spectrum block comprises a possible signal; adjusting the tuner to scan a second spectrum block with a second center frequency as the center according to a first rise point and a first drop point when it is determined that the first spectrum block comprises the possible signal; and determining whether the second spectrum block comprises a valid signal.

Abstract: An electronic device includes a receiving unit, a signal processing unit, a transmitting unit, and an audio timing unit. The receiving unit receives audio data and first video data. The signal processing unit generates second video data and a pixel clock signal for playing the second video data according to the first video data. The transmitting unit transmits the second video data, the audio data, the pixel clock signal, and a cycle time stamp (CTS) to a receiver. The audio timing unit generates an internal reference signal adjusts a frequency of the internal reference signal according to a receiving speed of the audio data, and generates the CTS according to the internal reference signal and the pixel clock signal so that the receiver can generate an audio clock signal for playing the audio data according to the pixel clock signal and the CTS.

Abstract: The present invention provides an encoder including a quantization circuit, a control circuit and an encoding circuit is disclosed. The quantization circuit is configured to generate quantized data corresponding to a CTU according to image data, wherein the CTU comprises at least one TU. The control circuit is configured to determine a number of allocated bits for each TU in the CTU, where the number of allocated bits for each TU is determined based on a sum of remaining bits of the TUs that have been encoded. The encoding circuit is configured to encode each TU to obtain encoded data according to the number of allocated bits of the TU in the CTU.

Abstract: A communication device respectively establishes a plurality of wireless communication connections with a plurality of predetermined devices in an infrastructure network, and includes a wireless transceiver and a processor. The wireless transceiver transmits or receives wireless signals. The processor selects a spatial reuse mechanism, generates spatial reuse information according to the spatial reuse mechanism, and transmits at least one packet carrying the spatial reuse information to the predetermined devices. The spatial reuse information defines a pattern of a communication period. The communication period comprises a spatial reuse phase and a non-spatial reuse phase. The spatial reuse information comprises time information of at least one of the spatial reuse phase and the non-spatial reuse phase. In response to a selection of the spatial reuse mechanism, the processor suspends a wireless signal transmission with the predetermined devices during the spatial reuse phase.

Abstract: The present invention provides an encoder including a quantization circuit, an encoding circuit, an energy parameter calculation circuit and a quantization parameter determination circuit. The quantization circuit is configured to perform quantization operations on a plurality of CTUs in image data in sequence to generate quantized data respectively corresponding to the plurality of CTUs. The encoding circuit is configured to perform encoding operations on the quantized data of the plurality of CTUs in sequence to generate encoded data. The energy parameter calculation circuit is configured to receive the image data, and calculate a plurality of energy parameters respectively corresponding to the plurality of CTUs in the image data. The quantization parameter determination circuit is configured to determine a plurality of quantization parameters of the plurality of CTUs according to at least a portion of the plurality of energy parameters, for the quantization circuit to perform the quantization operations.

Abstract: A communication device for handling a Peak-to-Average Power Ratio (PAPR), includes a transforming module, configured to perform a first plurality of inverse fast Fourier transforms (IFFTs) on a plurality of coefficients in a scene according to a first inverse fast Fourier transform (IFFT) size and the scene, to obtain a plurality of results; a processing module, coupled to the transforming module, configured to obtain a plurality of norms of the plurality of results, and to obtain a plurality of values of the plurality of coefficients; and a transmitting module, coupled to the processing module, configured to perform a second plurality of IFFTs on a plurality of frequency-domain signals according to a second IFFT size, the plurality of coefficients with the plurality of values and the scene, to obtain a plurality of time-domain signals, wherein the second IFFT size is greater than the first IFFT size.

Abstract: The present invention provides an image processing circuit and associated image processing method. In the image processing circuit, a characteristic value calculation circuit is designed to calculate the plurality of characteristic values of consecutive-three-pixels with increasing/decreasing brightness, the plurality of left-side characteristic values of consecutive-three-pixels with increasing/decreasing brightness and the plurality of right-side characteristic values of consecutive-three-pixels with increasing/decreasing brightness, for the brightness adjustments. The adjusted brightness values of the present invention have sharper edges to improve the image quality.

Abstract: A calibrating device can mitigate the static mismatch error of a digital-to-analog converter (DAC), and includes a digital code generating circuit, the DAC, an analog-to-digital converter (ADC), a filter circuit, an indicating circuit, and a statistical circuit. The digital code generating circuit generates a digital code of N digital codes. The DAC generates an analog signal corresponding to one of N signal levels according to the digital code. The ADC generates a digital signal according to the analog signal. The filter circuit generates a gradient value according to the difference between the digital code and the digital signal. The indicating circuit generates a selection signal according to the digital code. The statistical circuit learns from the selection signal that the gradient value is corresponding to a Kth digital code of the N digital codes, and determines whether the Kth digital code should be adjusted according to the gradient value.

Abstract: The present invention discloses a power supply method having power management mechanism that includes the steps outlined below. Power request information of power requesting devices is retrieved to generate a to-be-powered device list and a requested power. Whether a current requesting device satisfy a power stable criteria and a power sufficient criteria is determined, The power stable criteria is satisfied when the power requesting devices each having a priority higher than that of the current requesting device all operate in a powered mode or when the power requesting devices that operate in the powered mode enter a stable operation status. The power sufficient criteria is satisfied when a stable system remained power of a power supply system is not smaller than an individual requested power of the current requesting device. When the criteria are satisfied, the current requesting device is operated in the powered mode to update the requested power.

Abstract: A time-interleaved analog-to-digital converter (TIADC) operates in a first mode or a second mode and includes M analog-to-digital converters (ADCs), a reference ADC, a digital correction circuit, and a control circuit. The M ADCs sample an input signal according to M enable signals to generate M digital output codes. The reference ADC samples the input signal according to a reference enable signal to generate a reference digital output code. The digital correction circuit corrects the M digital output codes to generate M corrected digital output codes. The control circuit generates the M enable signals and the reference enable signal according to a clock. The control circuit outputs the M corrected digital output codes in turn but does not output the reference digital output code in the first mode and randomly outputs the M corrected digital output codes and the reference digital output code in the second mode.

Abstract: A method for exchanging messages is performed by a slave device, and includes: receiving a submission queue (SQ) tail doorbell from a host to learn that X SQ entries need to be processed, wherein “X” doesn't exceed a host SQ entry upper limit; performing multiple read operations according to the SQ tail doorbell to read the X SQ entries from the host, wherein the slave device reads Y SQ entries at most in each read operation, and “Y” is smaller than “X” and doesn't exceed a slave device SQ entry upper limit; preparing P completion queue (CQ) entries; performing multiple write operations to transmit the P CQ entries to the host, wherein the slave device transmits Q CQ entries at most in each write operation, and “Q” is smaller than “P” and doesn't exceed a slave device CQ entry upper limit; and transmitting a CQ tail doorbell to the host.

Abstract: A slew rate mitigation circuit includes a slew rate mitigation unit, a switch unit, and a control unit. The slew rate mitigation unit is configured to receive an input signal through an input terminal and generate an output signal at an output terminal at a mitigation rate according to the input signal. The switch unit is coupled between the input terminal and the output terminal. The control unit is configured to selectively turn on the switch unit according to the output signal. The switch unit builds a fast charging path from the input terminal to the output terminal when turned on and cuts off the fast charging path when turned off.

Abstract: The present invention provides a receiver including a decoder, an upscale circuit and a color space conversion circuit. The decoder is configured to decode a video stream to generate a base layer and an enhancement layer. The upscale circuit is configured to perform an upscaling operation on the base layer to generate an upscaled base layer, wherein the upscaled base layer comprises luminance values of a plurality of pixels of a frame, and the enhancement layer comprises residuals of the plurality of pixels of the frame. The color space conversion circuit is configured to use a conversion matrix to combine the upscaled base layer and the enhancement layer to generate output video data.

Abstract: The present invention provides a detection circuit including a neural network module and a calculation circuit is disclosed. The neural network module is configured to receive an image to generate an output tensor, wherein the output tensor includes position information of a specific object and distance adjustment information. The calculation circuit is coupled to the neural network module, and is configured to calculate an initial distance between an image capture device and the specific object according to the position information of the specific object, and generate an estimated distance according to the initial distance and the distance adjustment information.

Abstract: The present invention discloses an analog-to-digital conversion circuit having speed-up comparison mechanism. Each of a positive and a negative capacitor arrays receives a positive and a negative input voltages to generate a positive and a negative output voltages. A first comparator performs comparison thereon to generate a first comparison result and a second comparator performs comparison according to a reference voltage to generate a second comparison result. A control circuit switches a capacitor enabling combination of the capacitor arrays according to the first comparison result and outputs a digital code as a digital output signal when the positive and the negative output voltages equal. The control circuit operates in a speed-up switching mode when a difference between the positive and the negative output voltages is outside of a predetermined range defined by the reference voltage and operates in a normal switching mode when the difference is within the predetermined range.

Abstract: Disclosed is a data processing device including a main SoC, a performance-enhancing SoC, and an external circuit that is set outside any of the two SoCs. The main SoC includes: a first central processing unit (CPU) dividing to-be-processed data into a first input part and a second input part, and processing the first input part to generate first output data; and a first transceiver circuit forwarding the second input part to the performance-enhancing SoC via the external circuit, and then receiving second output data via the external circuit and forwarding it. The performance-enhancing SoC includes: a second transceiver circuit receiving the second input part via the external circuit, and transmitting the second output data to the main SoC via the external circuit; and a second CPU receiving the second input part from the second transceiver circuit and processing it to provide the second output data for the second transceiver circuit.

Abstract: A transconductance amplifier includes a first MOS transistor configured to receive a first voltage at a first node and output a first current to a fifth node in accordance with a third voltage at a third node; a second MOS transistor configured to receive a second voltage at a second node and output a second current to a sixth node in accordance with a fourth voltage at a fourth node; a third MOS transistor configured to output a third current to the third node in accordance with a fifth voltage at the fifth node; a fourth MOS transistor configured to output a fourth current to the fourth node in accordance with a sixth voltage at the sixth node; and a source degeneration network placed across the third node and the fourth node.

Abstract: A display control system includes a display and an electronic device. The display includes a display panel, a USB hub, and a display control circuit. The USB hub receives a control signal in a first format through a USB interface. The display control circuit receives a control signal in a second format from the USB hub and controls the display panel according to the control signal in the second format. The electronic device includes an input device, a USB driver circuit, and a processor circuit. The input device generates an input signal. The USB driver circuit is electrically coupled to the USB hub of the display through the USB interface. The processor circuit generates an original control signal according to the input signal and controls the USB driver circuit to transmit the control signal in the first format through the USB interface.

Abstract: A display updating system and a display are provided. The display updating system includes a display and an electronic device. The display includes a display panel, a USB hub, and a display control circuit. The USB hub is configured to receive a plurality of display program codes through a USB interface. The display control circuit is configured to receive the display program codes from the USB hub and store the display program codes. The electronic device is connected to the display through the USB interface and includes a memory, a USB driver circuit, and a calculation circuit. The memory is configured to store the display program codes. The USB driver circuit is connected to the USB hub of the display through the USB interface. The calculation circuit is configured to control the USB driver circuit to transmit the display program codes through the USB interface.