Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10707894
    Abstract: A modulator includes an analog integrator including an analog circuit and a quantizer quantizing its output signal. An external input signal is input thereto. A modulator is coupled to the latter stage of the modulator, and includes a quantizer. A probe signal generation circuit injects a probe signal to the modulator. An adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with a probe signal. Another adaptive filter searches for a transfer function of the modulator by observing an output signal of the quantizer in accordance with the probe signal. A noise cancel circuit cancels a quantization error generated by the quantizer using search results of the adaptive filters.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Oshima, Tetsuo Matsui, Mitsuya Fukazawa, Tomohiko Yano
  • Patent number: 10707762
    Abstract: An object of the present invention is to provide a power supply voltage stabilizing method that can suppress the performance of switching power supply from being deteriorated even when a battery voltage varies and/or load conditions change. In a power supply voltage stabilizing method of a switching power supply including an output power MOS to which a battery voltage is supplied and a PWM feedback control unit that controls the output power MOS, the PWM feedback control unit includes a voltage feedback controller that controls on the basis of a power supply voltage output from the switching power supply and a current feedback controller that controls on the basis of a current output from the switching power supply. A variation in the battery voltage and/or a change in the load condition of the switching power supply are/is detected, and the bandwidth of the PWM feedback control unit is dynamically changed in accordance with the result of the detection.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masayuki Ida
  • Patent number: 10706917
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
  • Patent number: 10706178
    Abstract: According to one embodiment, a data processing apparatus includes an access controller configured to control access by a CPU to a processor. The access controller selects permission configuration information and an identifier table to be used for the access control using processor selection information output from the CPU, determines as intermediate identifier MID that corresponds to an access request identifier SPID output from the CPU using the selected identifier table, and determines accessibility of the CPU to the processor using the selected permission configuration information and the determined intermediate identifier MID.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Sugita, Koji Adachi, Yoichi Yuyama
  • Patent number: 10707223
    Abstract: Characteristics of a semiconductor device having a nonvolatile memory are improved. A high dielectric constant film is provided on an insulating film between a memory gate electrode and a fin as components of a nonvolatile memory. The high dielectric constant film is provided over the top of the fin and the top of an element isolation region, but is not provided over a side surface of the fin. In this way, since the high dielectric constant film is provided over the top of the fin and the top of the element isolation region, it is possible to relax an electric field in the vicinity of each of the upper and lower corner portions of the fin, leading to an improvement in disturbance characteristics.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shunichi Narumi
  • Publication number: 20200212176
    Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto KOSHIMIZU, Hideki NIWAYAMA, Kazuyuki UMEZU, Hiroki SOEDA, Atsushi TACHIGAMI, Takeshi IIJIMA
  • Patent number: 10700519
    Abstract: A power supply system includes a plurality of voltage sources, a switch circuit that switches between a state in which the plurality of voltage sources are connected in series and a state in which the plurality of voltage sources are connected in parallel, and a voltage control circuit that boosts an input voltage. The switch circuit connects the plurality of voltage sources in series, supplies an output of the plurality of serially connected voltage sources to an output node of the voltage control circuit, thereafter connects the plurality of voltage sources in parallel, and supplies outputs of the plurality of parallel-connected voltage sources to the voltage control circuit, and the voltage control circuit boosts voltages of the plurality of parallel-connected voltage sources.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 30, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshifumi Ikenaga
  • Patent number: 10700693
    Abstract: The analog-to-digital converter includes a quantizer for outputting a quantized signal, a sampling circuit for sampling an analog input signal, a dithering circuit for generating an added voltage, and an integrating circuit for integrating a signal on which the added voltage is superimposed and outputting an integration result to the quantizer. The dithering circuit includes a variable capacitance circuit and a control circuit. The variable capacitance circuit includes a plurality of capacitors. The control circuit controls the capacitance of the variable capacitance circuit to a capacitance smaller than the capacitances of the capacitors, and causes the variable capacitance circuit to generate an added voltage.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 30, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akemi Watanabe
  • Patent number: 10692878
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: June 23, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
  • Patent number: 10693396
    Abstract: To surely detect a back electromotive force generated in a non-conduction phase at an extremely low duty ratio, a motor driving system includes a three-phase motor, an inverter circuit, and a semiconductor device. A controller included in the semiconductor device compares a voltage at an output node corresponding to a non-conduction phase of the inverter circuit and a reference voltage with each other, thereby estimating a position of a rotor of the three-phase motor and generating a pulse width modulation signal based on the estimated position of the rotor. The controller detects the voltage at the output node of the non-conduction phase in a regeneration period of the pulse width modulation signal when a duty ratio of the pulse width modulation signal is less than a threshold value, the regeneration period being a period in which current is made to flow to the three-phase motor on a regeneration path.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 23, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Satoshi Narumi
  • Patent number: 10693476
    Abstract: Increases of circuit scale and power consumption are suppressed while frequency deviation is kept within a predetermined allowable range. A semiconductor device according to an embodiment includes a variable load capacity circuit including a plurality of load capacity elements coupled in parallel to one end of a crystal resonator and a plurality of switches that are respectively serially coupled to the load capacity elements, and a switch control unit that controls ON/OFF of the switches on the basis of information to be an index of frequency deviation due to temperature change of a frequency signal obtained by oscillating the crystal resonator. The switch control unit changes the number of switches that will be turned ON among the plurality of switches so that an absolute value of the frequency deviation becomes small when the information is not included in a predetermined allowable range.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 23, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Maruyama, Noriaki Matsuno
  • Publication number: 20200186748
    Abstract: A photographing control device capable of storing images to be stored at appropriate timings is provided. The analysis result acquiring unit acquires an analysis result of an image obtained by photographing an object by the photographing device. The status acquisition unit acquires a detection result obtained by detecting the status of the object by the sensor. The index determination unit determines the degree of these indexes for each of a plurality of indexes including those relating to the object based on the image analysis result and the detection result of the state of the object. The evaluation value calculation unit calculates an evaluation value for evaluating the stored value of the image using the degree of the index. When the evaluation value exceeds a predetermined threshold value, the image storage control unit 15 controls so as to store an image.
    Type: Application
    Filed: October 17, 2019
    Publication date: June 11, 2020
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehito BABA
  • Patent number: 10680071
    Abstract: To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 9, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Tadashi Yamaguchi
  • Patent number: 10677844
    Abstract: A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to a an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: June 9, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Iwao Suzuki, Naoki Kato
  • Patent number: 10679102
    Abstract: An abnormality detection apparatus includes a feature extraction unit configured to extract an image feature according to a common algorithm, a flow calculation unit, a first abnormality detection unit, and a second abnormality detection unit. An extraction range for the image feature is composed of a predetermined first partial area in a first image, a predetermined second partial area in a second image, and areas near places in the first and second images predicted as destinations of the feature point. The first abnormality detection unit detects an abnormality in the first (second) image based on an optical flow for a feature point in the first (second) partial area. The second abnormality detection unit detects an abnormality by using a feature point in a first overlapped extraction area defined in a first overlapped area and a feature point in a second overlapped extraction area defined in a second overlapped area.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: June 9, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Kajiwara, Kosuke Miyagawa, Masaki Nishibu, Kentaro Sasahara
  • Publication number: 20200174641
    Abstract: An object of the present invention is to provide an information input device capable of realizing high-precision touch operations. The information input device includes a first surface for displaying input request information, a second surface for inputting input request information, a viewpoint calculator for calculating a viewpoint direction of an input person, and a coordinate corrector for correcting a position input to the second surface into a second position in response to the viewpoint direction of the input person and inputs the input request information on the first surface corresponding to the second position. The information input device further provides a storage device for holding distance information on distance between the first surface and the second surface.
    Type: Application
    Filed: October 8, 2019
    Publication date: June 4, 2020
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Kentarou NIIKURA
  • Patent number: 10672750
    Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoichiro Kurita
  • Patent number: 10672360
    Abstract: A display data correction apparatus is provided with: a control circuit responsive to an input gray-level value for initially providing first to N-th control points (N?3) defined in a coordinate system in which a first coordinate axis is associated with the input gray-level value and a second coordinate axis is associated with an output gray-level value to be calculated for the input gray-level value; and a processing circuit obtaining an output gray-level value by repeating an update operation in which the first to N-th control points are updated. The degree (N?1) Bezier curve is used as an approximated curve of the gamma curve. The output gray-level value is finally obtained as the coordinate value of a specific point in the degree (N?1) Bezier curve along the second coordinate axis, where the specific point has the coordinate value closest to the input gray-level value along the first coordinate axis.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirobumi Furihata, Takashi Nose
  • Patent number: 10672897
    Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata
  • Patent number: 10672463
    Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi