Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10700519
    Abstract: A power supply system includes a plurality of voltage sources, a switch circuit that switches between a state in which the plurality of voltage sources are connected in series and a state in which the plurality of voltage sources are connected in parallel, and a voltage control circuit that boosts an input voltage. The switch circuit connects the plurality of voltage sources in series, supplies an output of the plurality of serially connected voltage sources to an output node of the voltage control circuit, thereafter connects the plurality of voltage sources in parallel, and supplies outputs of the plurality of parallel-connected voltage sources to the voltage control circuit, and the voltage control circuit boosts voltages of the plurality of parallel-connected voltage sources.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 30, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshifumi Ikenaga
  • Patent number: 10700693
    Abstract: The analog-to-digital converter includes a quantizer for outputting a quantized signal, a sampling circuit for sampling an analog input signal, a dithering circuit for generating an added voltage, and an integrating circuit for integrating a signal on which the added voltage is superimposed and outputting an integration result to the quantizer. The dithering circuit includes a variable capacitance circuit and a control circuit. The variable capacitance circuit includes a plurality of capacitors. The control circuit controls the capacitance of the variable capacitance circuit to a capacitance smaller than the capacitances of the capacitors, and causes the variable capacitance circuit to generate an added voltage.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: June 30, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akemi Watanabe
  • Patent number: 10692878
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: June 23, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
  • Patent number: 10693396
    Abstract: To surely detect a back electromotive force generated in a non-conduction phase at an extremely low duty ratio, a motor driving system includes a three-phase motor, an inverter circuit, and a semiconductor device. A controller included in the semiconductor device compares a voltage at an output node corresponding to a non-conduction phase of the inverter circuit and a reference voltage with each other, thereby estimating a position of a rotor of the three-phase motor and generating a pulse width modulation signal based on the estimated position of the rotor. The controller detects the voltage at the output node of the non-conduction phase in a regeneration period of the pulse width modulation signal when a duty ratio of the pulse width modulation signal is less than a threshold value, the regeneration period being a period in which current is made to flow to the three-phase motor on a regeneration path.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 23, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Satoshi Narumi
  • Patent number: 10693476
    Abstract: Increases of circuit scale and power consumption are suppressed while frequency deviation is kept within a predetermined allowable range. A semiconductor device according to an embodiment includes a variable load capacity circuit including a plurality of load capacity elements coupled in parallel to one end of a crystal resonator and a plurality of switches that are respectively serially coupled to the load capacity elements, and a switch control unit that controls ON/OFF of the switches on the basis of information to be an index of frequency deviation due to temperature change of a frequency signal obtained by oscillating the crystal resonator. The switch control unit changes the number of switches that will be turned ON among the plurality of switches so that an absolute value of the frequency deviation becomes small when the information is not included in a predetermined allowable range.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 23, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Maruyama, Noriaki Matsuno
  • Publication number: 20200186748
    Abstract: A photographing control device capable of storing images to be stored at appropriate timings is provided. The analysis result acquiring unit acquires an analysis result of an image obtained by photographing an object by the photographing device. The status acquisition unit acquires a detection result obtained by detecting the status of the object by the sensor. The index determination unit determines the degree of these indexes for each of a plurality of indexes including those relating to the object based on the image analysis result and the detection result of the state of the object. The evaluation value calculation unit calculates an evaluation value for evaluating the stored value of the image using the degree of the index. When the evaluation value exceeds a predetermined threshold value, the image storage control unit 15 controls so as to store an image.
    Type: Application
    Filed: October 17, 2019
    Publication date: June 11, 2020
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehito BABA
  • Patent number: 10679102
    Abstract: An abnormality detection apparatus includes a feature extraction unit configured to extract an image feature according to a common algorithm, a flow calculation unit, a first abnormality detection unit, and a second abnormality detection unit. An extraction range for the image feature is composed of a predetermined first partial area in a first image, a predetermined second partial area in a second image, and areas near places in the first and second images predicted as destinations of the feature point. The first abnormality detection unit detects an abnormality in the first (second) image based on an optical flow for a feature point in the first (second) partial area. The second abnormality detection unit detects an abnormality by using a feature point in a first overlapped extraction area defined in a first overlapped area and a feature point in a second overlapped extraction area defined in a second overlapped area.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: June 9, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Kajiwara, Kosuke Miyagawa, Masaki Nishibu, Kentaro Sasahara
  • Patent number: 10677844
    Abstract: A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to a an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: June 9, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Iwao Suzuki, Naoki Kato
  • Patent number: 10680071
    Abstract: To allow a metal oxide film composed mainly of O and at least one of Hf and Zr to exhibit ferroelectric properties. After deposition of a hafnium oxide film on a semiconductor substrate via an insulating film, the semiconductor substrate is exposed to microwaves to selectively heat the hafnium oxide film. This makes it possible to form a larger number of orthorhombic crystals in the crystals of the hafnium oxide film. The hafnium oxide film thus obtained can therefore exhibit ferroelectric properties without adding, thereto, an impurity such as Si. This means that the hafnium oxide film having a reverse size effect can be used as a ferroelectric film of a ferroelectric memory cell and contributes to the manufacture of a miniaturized ferroelectric memory cell.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 9, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Tadashi Yamaguchi
  • Publication number: 20200174641
    Abstract: An object of the present invention is to provide an information input device capable of realizing high-precision touch operations. The information input device includes a first surface for displaying input request information, a second surface for inputting input request information, a viewpoint calculator for calculating a viewpoint direction of an input person, and a coordinate corrector for correcting a position input to the second surface into a second position in response to the viewpoint direction of the input person and inputs the input request information on the first surface corresponding to the second position. The information input device further provides a storage device for holding distance information on distance between the first surface and the second surface.
    Type: Application
    Filed: October 8, 2019
    Publication date: June 4, 2020
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Kentarou NIIKURA
  • Patent number: 10671467
    Abstract: The aim of the present disclosure is to provide a watchdog timer that can perform a fault diagnosis during the actual use of a semiconductor device. In a semiconductor device provided with a watchdog timer, the watchdog timer includes a counter; a counter control circuit that changes a count value of the counter to a desired value in the refresh period of the count value; and a fault diagnosis module. The fault diagnosis module includes a suppressing circuit that suppresses generation of a reset signal to the exterior of the watchdog timer in the refresh period; and a holding circuit that holds the reset signal.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuhito Ebisawa, Yukihiro Kishida
  • Patent number: 10672916
    Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masao Inoue
  • Patent number: 10672725
    Abstract: The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Vias are formed in each layer on a dicing region side. The vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuo Tomita
  • Patent number: 10672463
    Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Patent number: 10672360
    Abstract: A display data correction apparatus is provided with: a control circuit responsive to an input gray-level value for initially providing first to N-th control points (N?3) defined in a coordinate system in which a first coordinate axis is associated with the input gray-level value and a second coordinate axis is associated with an output gray-level value to be calculated for the input gray-level value; and a processing circuit obtaining an output gray-level value by repeating an update operation in which the first to N-th control points are updated. The degree (N?1) Bezier curve is used as an approximated curve of the gamma curve. The output gray-level value is finally obtained as the coordinate value of a specific point in the degree (N?1) Bezier curve along the second coordinate axis, where the specific point has the coordinate value closest to the input gray-level value along the first coordinate axis.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirobumi Furihata, Takashi Nose
  • Patent number: 10672750
    Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoichiro Kurita
  • Patent number: 10672897
    Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata
  • Patent number: 10670478
    Abstract: It is possible to detect a failure in a temperature sensor while preventing enlarging of a circuit scale. A temperature measurement circuit 10 includes temperature sensors 20 and 30, and a comparator 40. The temperature sensor 20 includes a temperature detection unit 21 including a resistive element, a resistance value of which varies in accordance with temperature changes, and an AD converter which converts a voltage of the temperature detection unit 21 into a temperature digital value D1. The temperature sensor 30 includes a ring oscillator 31 which oscillates at a cycle that is temperature dependent, and generates a digital value D2 based on an oscillating signal output by the ring oscillator 31. The comparator 40 compares the temperature digital values D1 and D2, and outputs a signal indicating whether the temperature sensor 20 is normal or not based on a comparison result.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 2, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Chiaki Kumahara, Tetsuhiro Koyama, Masaaki Hirano
  • Patent number: 10664180
    Abstract: It is possible to prevent a central processing unit and a security processing unit from accessing of a non-volatile memory at the same time. A data flash 13 includes a secure area 31 and a user area 32. In the secure area 31, a plurality of pieces of security information used in a security process is stored. A security IP 12 reads out a portion of the plurality of pieces of security information from the secure area 31 and stores it in the secure RAM 22. When the security information to be used in the security process is stored in the secure RAM, the security IP 12 reads out the security information from the secure RAM 22 and uses it.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 26, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinsuke Asari, Kenichi Ito, Yuki Mori, Shigemasa Shiota
  • Patent number: 10664370
    Abstract: Related semiconductor devices have a problem in which analysis processing with high defect reproducibility cannot be performed. According to an embodiment, a semiconductor device includes a first arithmetic core that executes a first program stored in a first code area using a first local memory area and a second arithmetic core that executes a second program stored in a second code area using a second local memory area. In an analysis mode, the semiconductor device performs first analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the first program and second analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the second program, and compares a plurality of arithmetic result data pieces acquired from the first and second analysis processing to thereby acquire analysis information used for defect analysis.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: May 26, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenji Shiozawa, Yoshihide Nakamura, Takuya Lee, Yutaka Nakadai, Tetsuya Kokubun, Hiroyuki Sasaki