Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10998408
    Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 4, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tadashi Yamaguchi
  • Patent number: 10996877
    Abstract: Limitations on memory access decrease the computing capability of related-art semiconductor devices during convolution processing in a convolutional neural network. A semiconductor device according to an aspect of the present invention includes an accelerator section that performs computation on a plurality of intermediate layers included in a convolutional neural network by using a memory having a plurality of banks capable of changing the read/write status on an individual bank basis. The accelerator section includes a network layer control section that controls a memory control section in such a manner as to change the read/write status assigned to the banks storing input data or output data of the intermediate layers in accordance with the transfer amounts and transfer rates of the input data and output data of the intermediate layers included in the convolutional neural network.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 4, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Manabu Sasamoto, Atsushi Nakamura, Hanno Lieske, Shigeru Matsuo
  • Patent number: 10992223
    Abstract: A semiconductor device capable of stabilizing an internal voltage is provided. According to one embodiment, the semiconductor device comprises a stabilized power supply circuit for generating a first voltage, a charge pump circuit for generating a second voltage different from the first voltage using the first voltage, the COUT2 including a comparison circuit for comparing the second voltage with a reference voltage, and a dummy load circuit controlled to be turned on or off in response to a comparison result signal COUT2 outputted from the comparison circuit, and the Dummy load circuit receives the comparison result signal COUT2 and is turned on for a predetermined period, whereby at least a part of a current IDD based on the first voltage flows into the dummy load circuit.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 27, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hidetoshi Ozoe
  • Patent number: 10992295
    Abstract: A monolithic integrated circuit for controlling a high-side switching element for a load using a bootstrap capacitor is disclosed. The integrated circuit comprises a first supply voltage input for receiving a first input supply voltage V1, a second supply voltage input for receiving a second, current-limited input supply voltage VCP, a voltage-sensing input for receiving a source voltage, a first output for providing a drive signal VG to the switching element, a second output for providing a charging signal VBS to a bootstrap capacitor, a pre-driver for generating the drive signal, the pre-driver having a voltage input and an output which is coupled to the first output, and a power supply control section comprising first and second switches. The first and second switches are arranged in series between the first input and the second output, the second input is coupled to a node between the first and second switches, and the second node is coupled to a voltage input of the pre-driver.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: April 27, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hans-Juergen Braun
  • Patent number: 10992167
    Abstract: To extend the transmission distance with the voltage supply source and improve the communication performance of PLCs Solution. The power supply circuit includes a step-down DC/DC converter to which a voltage supplied from the power line is input and to which an input voltage is stepped down and output, a step-up/down DC/DC converter to which a voltage output from the step-down DC/DC converter or a voltage supplied from the power line is input and to which the input voltage is stepped up or stepped down and output to the power line communication circuit, a switch circuit for connecting an input of the step-up/down DC/DC converter to an output of the step-down DC/DC converter or power line, a voltage monitoring circuit for monitoring a voltage supplied from the power line, and a control circuit for controlling connection of the switch circuit based on the voltage value of the voltage supplied from the power line.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: April 27, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Noriyuki Shinohara, Akira Kuwano
  • Patent number: 10991709
    Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: April 27, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10991653
    Abstract: In a semiconductor device, a semiconductor substrate includes a bulk layer, a buried oxide layer provided in at least a partial region on the bulk layer, and a surface single crystal layer on the buried oxide layer. An inductor is provided above a main surface side of the semiconductor substrate on which the surface single crystal layer is disposed. To increase a Q value of the inductor, a ground shield is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: April 27, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Uchida, Yasutaka Nakashiba
  • Patent number: 10986373
    Abstract: An image encoding device includes an encoding circuit configured to encode an image, the image being constituted of a plurality of columns and a plurality of rows of which width are longer than the columns, generate a reference image and stores the reference image into a memory, and output a bit stream including the encoded image. The image encoding device also includes an image rotation circuit configured to rotate the image read from the memory by 90° and output the rotated image to a encoding processing circuit, and a read address generating circuit configured to read the column of the image from the memory, and provide the column with the image rotation circuit.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: April 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Kazushi Akie, Tetsuya Shibayama, Kenichi Iwata
  • Patent number: 10984742
    Abstract: A display control device comprises an output unit that outputs an inverted polarity of an AC signal in a constant cycle, based on a signal of the constant cycle; a stop control unit that stops the reversal of the polarity of the AC signal in the output unit, based on a stop signal; a rewrite control unit for outputting a display data rewrite signal; and a transmission control unit for controlling the rewrite control unit. The stop signal stops the reversal of the polarity of the AC signal during a period in which the display data rewrite signal is output. The AC signal stopped by the stop signal maintains a polarity before the stop of polarity reversal. The output unit inverts and outputs the polarity of the AC signal, based on the signal of the constant cycle, after a period in which the display data rewrite signal is output.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhiro Nagasawa
  • Patent number: 10982977
    Abstract: A pulse signal generator suitable for generating a two-phase pulse signal required as information of a rotation angle of a motor from a motor control device is provided. According to an embodiment, the pulse signal generator includes: a compensation unit that outputs a compensation signal for compensating for the deviation between the angle information representing the rotation angle of the rotor provided in the resolver and the fed back angle information; a counter pulse output unit that outputs a counter pulse having a frequency corresponding to the compensation amount of the compensation signal and code information representing the sign of the compensation signal, and a pulse processing unit that outputs a count value by a counter as the angle information, which counts the pulse according to the code information, the pulse processing unit generating two-phase pulse signals PA and PB using the values of the counter.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Shimada, Yuji Shimizu, Yutaka Ono
  • Patent number: 10985012
    Abstract: First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhiko Segi
  • Patent number: 10983924
    Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: April 20, 2021
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Kondoh
  • Publication number: 20210109383
    Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 15, 2021
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka NAKASHIBA, Tohru KAWAI
  • Patent number: 10978308
    Abstract: method of manufacturing a semiconductor device capable of manufacturing a miniaturized semiconductor device is provided. The method of manufacturing a semiconductor device according to an embodiment includes the steps of: preparing a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; forming a hard mask having an opening on the first surface; forming a gate trench extending toward the second surface on the first surface using the hard mask as a mask; widening the width of the opening; filling the opening with an interlayer insulating film; and forming a contact hole in the interlayer insulating film by removing the hard mask.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: April 13, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masaaki Kanazawa
  • Patent number: 10978154
    Abstract: A semiconductor device includes first and second voltage control lines for a first memory block and third and fourth voltage control lines for a second memory block, for driving gate lines for memory transistors; a first decoder driving the first and third voltage control lines; a second decoder driving the second and fourth voltage control lines; and a control circuit controlling a voltage for the first and second decoders. The control circuit supplies a first voltage and a second voltage lower than the first voltage to the first decoder and a third voltage between the first and second voltages, and the second voltage to the second decoder, before writing operation; and supplies the first voltage and the third voltage to the first decoder and a fourth voltage between the third and second voltages, and a fifth voltage lower than the second voltage to the second decoder, in the writing operation.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 13, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoji Kashihara
  • Patent number: 10978394
    Abstract: In the semiconductor device, a first defect formation preventing film is formed on the first wiring side, and a second defect formation preventing film is formed on the second wiring side. when a ratio of an infrared absorption intensity corresponding to a bond between silicon and hydrogen to an infrared absorption intensity corresponding to a bond between silicon and oxygen is defined as an abundance ratio, the abundance ratio in the first defect formation preventing film is smaller than the abundance ratio in the second interlayer insulating film. The abundance ratio in the second defect formation preventing film is smaller than the abundance ratio in the second interlayer insulating film.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: April 13, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naohito Suzumura, Kazuyuki Omori
  • Patent number: 10978505
    Abstract: A hybrid-bonding-type solid-state imaging device is provided that prevents moisture from entering through the bonded interface and other areas. The solid-state imaging device includes a first interconnect structure over a sensor substrate and a second interconnect structure over a logic substrate, and the first and second interconnect structures are bonded together. At the bonded surface between the first and second interconnect structures, bonding pads formed in the first interconnect structure are bonded to bonding pads formed in the second interconnect structure. Eighth layer portions of a first seal ring formed in the first interconnect structure are bonded to eighth layer portions of a second seal ring formed in the second interconnect structure.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: April 13, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hidenori Sato, Koji Iizuka, Takeshi Kamino
  • Patent number: 10978385
    Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 13, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 10974719
    Abstract: A mobile object control system has an SfM unit detecting distance to an object imaged by a monocular camera by using the SfM algorithm, a first-stop-position output unit outputting a first stop position, a second-stop-position calculating unit calculating a second stop position closer than the first stop position, and a control unit controlling travel of a mobile object. The control unit controls the mobile object so as to stop at the second stop position. When a predetermined starting condition is satisfied, the control unit controls the mobile object so as to start. The SfM unit detects the distance to an object by using an image captured by the monocular camera after the mobile object starts. When a result of detection of the distance of the object by the SfM unit is obtained, the control unit uses the detection result for control of the travel.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: April 13, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuaki Terashima, Yuki Kajiwara
  • Patent number: 10977834
    Abstract: The present invention provides a semiconductor device enabling efficient compression without increasing the circuit size and a processing method using the semiconductor device. According to an embodiment, an image processor includes: a coding circuit to perform image processing on a target image divided into a plurality of tiles, the image processing being performed on each of the tiles; a determination circuit to determine whether a tile boundary is included in the area of an image block serving as a unit of compression of the target image; and a compression circuit to compress the image block image-processed by the coding circuit, according to a determination result of the determination circuit.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 13, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryoji Hashimoto, Keisuke Matsumoto, Nhat Van Huynh