Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10650883
    Abstract: In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Yamaki
  • Patent number: 10644009
    Abstract: To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Makoto Yabuuchi
  • Patent number: 10642596
    Abstract: An object of the present invention is to perform a program updating process without reconstructing a program using a pre-update program and an update differential program. An embedded device has a nonvolatile memory having a plurality of planes from/to which data can be read/written independently and an address translator performing address translation by using an address translation table. When an address obtained by decoding an instruction by a CPU is an address corresponding to a change part in a default program, the address translator translates the address to an address in which a differential program is disposed.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadaaki Tanimoto, Kesami Hagiwara, Naoyuki Morita
  • Patent number: 10642607
    Abstract: A determination apparatus includes a difference code generation section that generates a first difference code and a second difference code, the first difference code representing a set of code pieces in a first program that are different from code pieces in a second program, the second difference code representing a set of code pieces in the second program that are different from code pieces in the first program, a logical expression derivation section that performs predetermined conversion to derive a first logical expression from the first difference code and derive a second logical expression from the second difference code, and a determination section that, depending on whether the second logical expression includes the first logical expression, determines whether the first program in a predetermined embedded device is dynamically updatable to the second program.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadaaki Tanimoto, Naoyuki Morita
  • Patent number: 10644580
    Abstract: A power supply circuit capable of generating a stable output voltage is provided. According to one embodiment, the power supply circuit includes a comparison unit that compares the divided voltage corresponding to the external output voltage with each of the first reference voltage and the second reference voltage to output the comparison result, a NAND circuit that controls whether or not to output the clock signal based on the comparison result by the comparison unit, and a booster circuit that boosts the external output voltage when the clock signal is supplied via the NAND circuit.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kenichi Nagamatsu
  • Patent number: 10643960
    Abstract: A semiconductor device includes a semiconductor chip including a first circuit and a wiring substrate over which the semiconductor chip is mounted. The wiring substrate includes input signal wires transmitting an input signal to the semiconductor chip, output signal wires transmitting an output signal from the semiconductor chip, and first conductor planes supplied with a reference potential. When a wire cross-sectional area is defined as the cross-sectional area of each wire in a direction orthogonal to a direction in which the wire extends, the wire cross-sectional area of each input signal wire is smaller than the wire cross-sectional area of each output signal wire. In the thickness direction of the wiring substrate, each input signal wire is interposed between second conductor planes and third conductor planes each supplied with the reference potential. Between the output signal wires and the input signal wires, the third conductor planes are disposed.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Wataru Shiroi, Shinji Katayama, Keita Tsuchiya
  • Patent number: 10645420
    Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Seiji Mochizuki, Keisuke Matsumoto
  • Patent number: 10642768
    Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaru Hase, Tetsuji Tsuda, Naohiro Nishikawa, Yuki Inoue, Seiji Mochizuki, Katsushige Matsubara, Ren Imaoka
  • Patent number: 10644679
    Abstract: A level shift circuit includes a pulse signal generation unit generating first and second pulse signals with respect to an input signal, a first level conversion unit converting the first pulse signal at a first voltage to a third pulse signal at a second voltage, a second level conversion unit converting the second pulse signal at the first voltage to a fourth pulse signal at the second voltage, and a flip flop circuit making an output signal at the second voltage rise according to the third pulse signal, and making the output signal at the second voltage fall according to the fourth pulse signal. The pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the first pulse signal when the input signal rises and the second pulse signal when the input signal falls, based on a non-matching comparison result.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koichi Takeda
  • Patent number: 10643930
    Abstract: An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadatoshi Danno, Atsushi Nishikizawa, Hiroyuki Nakamura
  • Patent number: 10643939
    Abstract: A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction “X” and a plurality of sub-wiring units extending in a direction “Y”, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction “X” and a plurality of sub-wiring units extending in the direction “Y”, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction “X” between the main wiring units. To the end units, via wirings are coupled.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Keita Tsuchiya, Yoshitaka Okayasu, Wataru Shiroi
  • Patent number: 10644017
    Abstract: On the upper surface of a fin projecting from the upper surface of a semiconductor substrate, there are formed a control gate electrode through a gate insulating film and a memory gate electrode through a gate insulating film. A semiconductor region is formed in the fin beside the control gate electrode. On the semiconductor region, an insulating film, a first interlayer insulating film, and a second interlayer insulating film are formed. A plug reaching the semiconductor region is formed in the second interlayer insulating film, the first interlayer insulating film, and the insulating film. A cap film is formed between the control gate electrode and the interlayer insulating film, and the plug is positioned also right above the cap film.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro Yamashita
  • Patent number: 10638600
    Abstract: An electronic device according to one embodiment includes a wiring substrate, the wiring substrate having a first wiring connected to a first external terminal and a second wiring connected to a second external terminal and extending along the first wiring. Additionally, the above electronic device has a semiconductor device mounted on the above wiring substrate and electrically connected to each of the first and second wirings. Further, the above electronic device has a capacitor mounted on the above wiring substrate and electrically connected to the semiconductor device via each of the above first and second wirings. Furthermore, a distance between the above semiconductor device and capacitor is shorter than a distance between each of the above first and second external terminals and the above capacitor.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 28, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuaki Tsukuda, Akihiro Nakahara
  • Patent number: 10635538
    Abstract: A semiconductor device and method includes a configuration information storage memory that stores a plurality of configuration information items, a state transition management unit that selects any one of the plurality of configuration information items, and a data path unit that dynamically reconfigures a circuit according to the configuration information item selected by the state transition management unit. When a detection of a failure or no failure is made in any one of a plurality of logic circuit groups provided in the data path unit, the state transition management unit selects the configuration information item depending on a result of the detection.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshitaka Izawa, Katsumi Togawa, Takao Toi, Taro Fujii
  • Patent number: 10638148
    Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda, Tetsuya Shibayama
  • Patent number: 10630067
    Abstract: A semiconductor device is provided for measuring a voltage of each of plural unit cells series-coupled in multi-stage and configuring an assembled battery. The semiconductor device includes two terminals coupled to two nodes which are electrodes of a unit cell and coupled with other unit cells, and a voltage measurement circuit which measures the inter-terminal voltage between the two terminals. The device also includes a down-convert level shifter circuit which converts the inter-terminal voltage into a low-potential-side inter-terminal voltage based on a ground potential, and a comparator circuit which compares the converted low-potential-side inter-terminal voltage with a predetermined reference voltage.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshitaka Muramoto, Junko Kimura, Hirohiko Hayakawa
  • Patent number: 10627884
    Abstract: To safely stop a system even when an abnormality occurs in a power supply for a control circuit, a semiconductor device includes a control circuit, a first power supply that outputs a first voltage to be supplied to the control circuit as a power-supply voltage, a first voltage monitoring circuit that determines whether the first voltage is abnormal, a first switch that is coupled to the first power supply and the control circuit, and cuts off supply of the first voltage to the control circuit when it is determined that the first voltage is abnormal, and a power-supply switching circuit that is coupled to the control circuit and a second power supply, which outputs a second voltage to be supplied to a circuit to which power supply is supplied other than the control circuit as a power-supply voltage, and supplies the second voltage to the control circuit in a state where the supply of the first voltage to the control circuit is cut off.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masataka Motohashi, Yosuke Watanabe
  • Patent number: 10630522
    Abstract: To reduce a hardware circuit scale and a memory capacity in a communication system reducing a PAPR. A transmitter includes a transmission processing feedback type FIR filter configured to feed back data outputted from the last stage delay element of a plurality of delay elements included in an FIR filter to the first stage delay element and configured to set an initial value to a delay element in a predetermined position, of the delay elements, and performs transmission processing by using the transmission processing feedback type FIR filter. A receiver includes a reception processing feedback type FIR filter configured similarly to the transmission processing feedback type FIR filter and performs reception processing by using the reception processing feedback type FIR filter.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirofumi Nakano, Yoshitaka Shibuya
  • Patent number: 10629704
    Abstract: A semiconductor device in which the retention characteristics of a rewritable memory cell packaged together with a field effect transistor including a metal gate electrode are improved and a method for manufacturing the semiconductor device. The semiconductor device includes a field effect transistor with a metal gate electrode and a rewritable memory cell. The manufacturing method includes the step of replacing a dummy gate electrode with the metal gate electrode. Before the step of replacing the dummy gate electrode with the metal gate electrode, the method includes the steps of making the height of the memory cell lower than the height of the dummy gate electrode and forming a protective film for covering the memory cell.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10629264
    Abstract: A content addressable memory includes a plurality of TCAM cells which configure one entry, a first word line coupled to the TCAM cells, a second word line coupled to the TCAM cells and a match line coupled to the TCAM cells and further includes a valid cell which stores a valid bit which indicates validity or invalidity of the entry, a bit line coupled to the valid line and a selection circuit which is coupled to the first word line and the second word line and sets the valid cell to a selected state in accordance with a situation where the first word line or the second word line is set to the selected state.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yohei Sawada, Makoto Yabuuchi, Masao Morimoto