Abstract: A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor.

Abstract: A data driver including an output circuit configured to output an output signal, and a driver output terminal configured to be connected with a display panel and provide the output signal to the display panel. The output circuit includes a buffer having an output coupled with an input of a first switch and an input of a second switch, an output protective resistor coupled between the driver output terminal and an output of the second switch, and a compensation resistor coupled in series with the first switch and between the output of the buffer and the output protective resistor.

Abstract: A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP.

Abstract: To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads 17 having a relatively small planar area, spaced apart from an adjacent connection pad 17 in each of partitioned regions, dishing generated in the connection pad 17 is lightened. In addition, by not forming a through hole 23 for forming a through electrode 27 in an interlayer insulating film 9 covering a semiconductor element, intrusion of H2O, a metal ion such as Na+ or K+, etc. into an element-forming region from the through hole, via the interlayer insulating film is prevented.

Abstract: A level shift circuit includes: a latch circuit (Q5, Q6, Q7, Q8) including first (Q5, Q7) and second (Q6, Q8) inverter circuits; a first input MOS transistor (Q1) operating in accordance with an input signal; a second input MOS transistor (Q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control MOS transistor (Q9). The latch circuit (Q5, Q6, Q7, Q8) outputs a voltage having been converted from the input voltage in level. Each of the first and second input MOS transistors (Q1, Q2) receives the input signal at its gate terminal, and drives the latch circuit (Q5, Q6, Q7, Q8) in accordance with the input signal. The current-voltage control MOS transistor (Q9) is provided between the input MOS transistor (Q1, Q2) and the latch circuit (Q5, Q6, Q7, Q8), and is driven in accordance with an inversion operation of the latch circuit by receiving an input of the control voltage at its gate terminal.

Abstract: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

Abstract: Conventional semiconductor devices disadvantageously failed to sufficiently enlarge a dynamic range. A semiconductor device according to an embodiment includes a plurality of registers 21 to 26 that sets a gradient of a ramp signal. In the semiconductor device, the values in the registers 24 to 26 that are reflected in the gradient of the ramp signal are switched at predetermined timings, whereby a ramp signal with a gradient that changes at the predetermined timings is generated, and an analog-to-digital converter uses the ramp signal to convert pixel signals acquired from a pixel area into digital values.

Abstract: Disclosed is a signal processing apparatus that processes an input signal to accurately detect an abrupt change in the input signal in accordance with the degree of linear change of a phase component in a frequency domain. The signal processing apparatus includes a converter that converts the input signal into the phase component and an amplitude component in the frequency domain, a linearity calculator that calculates the linearity of the phase component in the frequency domain, and a determiner that determines presence of the abrupt change in the input signal based on the linearity calculated by the linearity calculator.

Abstract: A semiconductor device includes a die pad having an upper surface and a lower surface opposite to the upper surface, a semiconductor chip having a main surface and a back surface opposite to the main surface so that a plurality of electrode pads are formed on the main surface and being mounted on the die pad so that the back surface is opposite to the upper surface of the die pad, a plurality of leads arranged to be aligned on a side of the die pad, a first wire electrically connecting between a first electrode pad among the plurality of electrode pads of the semiconductor chip and a first lead among the plurality of leads, and a second wire having a diameter thicker than a diameter of the first wire and electrically connecting between a second electrode pad among the plurality of electrode pads of the semiconductor chip.

Abstract: A data processing device includes: a first power-on reset circuit; a second power-on reset circuit with higher power consumption and higher reset voltage accuracy than the first power-on reset circuit; a storage unit storing information for determining whether to keep the second power-on reset circuit in an active state or an inactive state; and a central processing unit initialized in response to respective outputs of the first and second power-on reset circuits and setting the information in the storage unit.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the semiconductor device that is capable of adequately reducing the influence of inter-wiring capacitance even when a photoelectric conversion element is progressively miniaturized. A plurality of transfer transistors each include a photoelectric conversion element and a signal output section. A plurality of other transistors include at least one signal input/output section that is electrically coupled to the transfer transistors. An interlayer insulating film is formed so as to cover the transfer transistors and the other transistors. A total of at least three of at least one signal output section of the transfer transistors and at least one signal input/output section of the other transistors are coupled by a coupling layer that includes a conductor filled into a groove formed in the interlayer insulating film.

Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.

Abstract: A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.

Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.

Abstract: The deposition rate of a porous insulation film is increased, and the film strength of the porous insulation film is improved. Two or more organic siloxane raw materials each having a cyclic SiO structure as a main skeleton thereof, and having mutually different structures, are vaporized, and transported with a carrier gas to a reactor (chamber), and an oxidant gas including an oxygen atom is added thereto. Thus, a porous insulation film is formed by a plasma CVD (Chemical Vapor Deposition) method or a plasma polymerization method in the reactor (chamber). In the step, the ratio of the flow rate of the added oxidant gas to the flow rate of the carrier gas is more than 0 and 0.08 or less.

Abstract: Disclosed is a signal processing device that reduces the influence of an interfering wave to suppress the deterioration of a BER even if narrow-band noise is included in a communication band. In the signal processing device, which is capable of performing an FFT and performing a window function process as preprocessing before the FFT and achieves OFDM demodulation, the window function process is skipped to perform an FFT on a received signal if the frequency of narrow-band noise included in the received signal coincides with the subcarrier frequency of OFDM within a predetermined range. If the frequencies do not coincide with each other, the FFT is performed after the window function process is performed on the received signal.

Abstract: To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.

Abstract: A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: High-accuracy magnetic measurement is performed by efficiently using nitrogen-vacancy pairs in all orientations. A magnetic measurement apparatus includes a diamond crystal and an image sensor. The diamond crystal has nitrogen-vacancy pairs. The image sensor detects the intensities of fluorescence generated by an exciting light applied to the diamond crystal by using a plurality of pixels. The nitrogen-vacancy pairs of the diamond crystal are made to one-to-one correspond to the pixels. The fluorescence generated by one nitrogen-vacancy pair is received by one pixel made to correspond to the nitrogen-vacancy pair.