Abstract: A dug portion (50) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle (42) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion (50) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion (50) is smaller than a thickness of the chip. When the thickness of the chip is 100 ?m or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle (42).

Abstract: A device controller, a peripheral device, and a power control method that enable buffers to be used efficiently and that enable power control to be performed on the basis of data amounts accumulated in the buffers are provided. A novel device controller includes an input buffer for accumulating data output from a host device, an output buffer for accumulating data output to the host device, a data communication section for transferring data between the input and output buffers and the host device, and a data buffer control section for modifying buffer allocation amounts to the input and output buffers on the basis of the data amount accumulated in at least one of the input and output buffers. The data buffer control section causes the data communication section to transition from a normal power consumption mode to a low power consumption mode when the data amount reaches a predetermined value.

Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract: A semiconductor device includes a signal input pad, a protection object circuit, a first connection node connected with the protection object circuit, a first resistance element connected between the signal input pad and the first connection node, a first protection circuit section arranged between a power supply line or a ground line and a second connection node between the signal input pad and the first resistance element, and a second protection circuit section. The second protection circuit section includes at least one of a first PMOS transistor having a source connected with the first connection node, a drain connected with the ground line and a gate and a back gate connected with the power supply line, and a first NMOS transistor having a source connected with said first connection node, a drain connected with the power supply line and a gate and a back gate connected with the ground line.

Abstract: A semiconductor device includes a lower wiring layer including a plurality of lower wirings, each of the lower wirings being elongated to run substantially parallel to a first direction, a metal-insulator-metal (MIM) capacitor formed above the plurality of lower wirings, the MIM capacitor comprising lower and upper electrodes and a capacity dielectric film interposed between the lower and upper electrodes, and an upper wiring layer formed above the MIM capacitor, the upper wiring layer including a plurality of upper wirings which are connected to the lower and upper electrodes through a plurality of first via plus and a plurality of second via plugs, respectively. Each of the plurality of first via plugs and the plurality of second via plugs are arranged parallel to the first direction, and the plurality of second via plus is arranged above portions between the lower wirings.

Abstract: The upper end of a gate electrode is situated below the surface of a semiconductor substrate. An insulating layer is formed over the gate electrode and over the semiconductor substrate situated at the periphery thereof. The insulating layer has a first insulating film and a low oxygen permeable insulating film. The first insulating film is, for example, an NSG film and the low oxygen permeable insulating film is, for example, an SiN film. Further, a second insulating film is formed over the low oxygen permeable insulating film. The second insulating film is, for example, a BPSG film. The TDDB resistance of a vertical MOS transistor is improved by processing with an oxidative atmosphere after forming the insulating layer. Further since the insulating layer has the low oxygen permeable insulating film, fluctuation of the threshold voltage of the vertical MOS transistor can be suppressed.

Abstract: A semiconductor device composed of a Group III nitride semiconductor has the following structure. A substrate has on it an n-type first semiconductor layer, an active layer, and a p-type second semiconductor layer in this order. Two first end faces are formed by cleavage and oppose each other in planar view. Two trenches extend to the two first end faces in the direction orthogonal to the first end faces in planar view. Bottoms of the trenches are positioned at least below the lower surface of the active layer. Second end faces are formed by laser scribing in the direction orthogonal to the first end faces and outside the trenches.

Abstract: SOI MOSFETs are used for the transistors for switching of an antenna switch and yet harmonic distortion is significantly reduced. Capacitance elements are respectively added to either the respective drains or gates of the transistors comprising the through MOSFET group of reception branch of the antenna switch. This makes the voltage amplitude between source and gate and that between drain and gate different from each other. As a result, the voltage dependence of source-drain parasitic capacitance becomes asymmetric with respect to the polarity of voltage. This asymmetry property produces signal distortion having similar asymmetry property. Therefore, the following can be implemented by setting it so that it has the same amplitude as that of second-harmonic waves arising from the voltage dependence of substrate capacitance and a phase opposite to that of the same: second-order harmonic distortion can be canceled out and thus second-order harmonic distortion can be reduced.

Abstract: A wireless device has two or more radio systems and SIM channels. At least a part of the first radio system can be shut down to reduce the power consumed by the device. This occurs if the first radio system is unable to obtain suitable service for the first SIM channel and the second radio system is at least one of (i) providing at least some service on the second SIM channel for the device, and (ii) capable of searching for service for the first radio system.

Abstract: A drive circuit that outputs low-voltage differential signals to an external load circuit, including: first and second nodes to which the external load circuit is connected; a first series circuit including first and second switching elements, connected in series using the first node as a common node; a second series circuit including third and fourth switching elements, connected in series using the second node as a common node; and a first current source that outputs a predetermined current to the first and second series circuits, in which a back gate of a transistor of a first conductivity type included in at least one of the first and third switching elements or the first current source is forward-biased.

Abstract: Disclosed here is a semiconductor integrated circuit device configured to suppress a voltage drop over the route for transmitting voltages from a power cut-off switch to a power cut-off region without lowering the degree of freedom in routing signal wires in that region. The semiconductor integrated circuit device includes a semiconductor chip in which the power cut-off switch and power cut-off region are provided. A reduction in the number of wiring channels in the power-cut off region is avoided by locating the power cut-off switch outside the power cut-off region. Over the substrate, a substrate-side feed line is formed to transmit a power-supply voltage from the semiconductor chip to outside thereof via the power cut-off switch, before introducing the voltage again into the chip to feed the power cut-off region, thus suppressing the voltage drop between the power cut-off switch and the power cut-off region.

Abstract: Provided is a semiconductor chip in which a first rewiring connection part located in the peripheral electrode pad or relatively close to the peripheral electrode pad in the V/G line and a second rewiring connection part located relatively distant from the peripheral electrode pad in the V/G line and having a lower potential than the first rewiring connection part before formation of a rewiring line are connected by the rewiring line. The semiconductor chip includes an inspection part for wafer test in the second rewiring connection part, a part on the V/G line close to the second rewiring connection part and having a lower potential than the first rewiring connection part before the rewiring line formation, or a conductive part extended from the V/G line to a proximity of the second rewiring connection part and having a lower potential than the first rewiring connection part before the rewiring line formation.

Abstract: An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized.

Abstract: A microcontroller includes a first voltage detector that detects whether a power supply voltage is equal to or lower than a first voltage value to generate a first signal, a second voltage detector that detects whether the power supply voltage is equal to or lower than a second voltage value to generate a second signal, the second voltage value being lower than the first voltage value, a real-time clock that includes a memory and a clock counter responsive to a clock signal, and a Central Processing Unit (CPU) that receives the first signal. The first voltage detector, the second voltage detector, the real-time clock and the CPU are formed on a single chip. The clock counter receives the second signal. The memory stores a first value according to a second signal, and stores a second value according to a setup of time information to the clock counter.

Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.

Abstract: Object of the invention is to reduce the on resistance between source and drain of a nitride semiconductor device. Between a nitride semiconductor layer lying between source and drain regions and a nitride semiconductor layer serving as an underlying layer, formed is a material having an electron affinity greater than that of these nitride semiconductor layers and having a lattice constant greater than that of the nitride semiconductor layer serving as an underlying layer. As a result, an electron density distribution of a channel formed below a gate insulating film and that of a two-dimensional electron gas formed in a region other than the gate portion, when a gate voltage is applied, can be made closer in the depth direction, leading to reduction in on resistance.

Abstract: A trench gate transistor whose gate changes depth intermittently in the gate width direction, has a first offset region and a second offset region formed below the source and drain, respectively. The first offset region and the second offset region are shallower where they contact the device isolation film than is the device isolation film in those areas. The first and second offset regions nevertheless extend below the bottom of the trench.

Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

Abstract: An imaging apparatus includes an imaging sensor, a control unit that instructs the imaging sensor to capture a first picture with a first charge accumulation time based on a light source having a first frequency and to capture a second picture with a second charge accumulation time based on a light source having a second frequency different from the first frequency, and a difference picture generation unit that generates a difference picture by using the first and second pictures.