Abstract: An output circuit includes a first output transistor disposed between a higher-potential power supply terminal and an external output terminal, a current flowing from the source of the first output transistor to the drain thereof being controlled on the basis of an external input signal; a second output transistor disposed between a lower-potential power supply terminal and the external output terminal, a current flowing from the source of the second output transistor to the drain thereof being controlled on the basis of an external input signal; and a clamping transistor having a first terminal and a control terminal, the first terminal and the control terminal being coupled to the gate of the first output transistor, and a second terminal coupled to the drain of the first output transistor.

Abstract: An inspection device of a semiconductor integrated circuit includes a drive unit that moves a probe card back and forth and from side to side, a storage unit that stores arrangement of the semiconductor integrated circuit and a shape of the pads, and a control unit that controls the drive unit. The control unit controls the drive unit, performs an apex detection processing pressing the probe pin to the semiconductor integrated circuit, detecting positions of the probe pin where conduction is detected or not detected, and calculating coordinates of one apex of a inspection pad from detected positions, and calculates central coordinates of the inspection pad from information of the shape of the inspection pad based on the coordinates of the apex of the inspection pad. The drive unit presses the probe pin to the calculated central coordinates of the inspection pad to perform inspection.

Abstract: An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch.

Abstract: A ground conductor is formed by a conductor pattern placed to a surface of a dielectric substrate, and includes a first and a second opening. A transmission line is formed over the dielectric substrate by the conductor pattern. The transmission line supplies a signal to a first and a second peripheral conductor respectively surrounding the first and the second opening. The first and second opening are arranged axis-symmetrically with respect to the transmission line. Opening areas of the first and the second opening are determined so that, due to loop currents supplied by the transmission line flowing through the first and the second peripheral conductor, a region including the first opening and the first peripheral conductor operates as a magnetic field radiation first loop radiating element, and a region including the second opening and the second peripheral conductor operates as a magnetic field radiation second loop radiating element.

Abstract: To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction.

Abstract: A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Abstract: In a semiconductor package, a stamp is provided on at least one of at least a pair of opposed sides on an outer peripheral portion in contact with an edge of the package, which is a blank space up to now. With this configuration, the amount of stamp can be increased even in a narrow stamp area.

Abstract: A power supply selection/detection circuit to select one main power supply from a plurality of external power supplies includes a resistance element with one end connected to an external power supply and another end connected to the main power supply, a first voltage detector to receive a voltage of the external power supply and detect a voltage of the external power supply, a second voltage detector to detect a voltage between the ends of the resistance element, and a switch connected between the external power supply and a ground to short-circuit or open-circuit between the external power supply and the ground according to an output of the second voltage detector. The resistance element and the first voltage detector are disposed for each of the plurality of external power supplies, and the second voltage detector and the switch are disposed for at least one of the plurality of external power supplies.

Abstract: A rear surface opposite to one plane of a die pad is formed to be exposed from one plane of a sealing resin. In addition, a concave portion disposed to be parallel with at least a first side of an outermost edge of a central structure and a second side adjacent to the first side, respectively, is formed in the one plane of the sealing resin. Here, a depth of the concave portion is equal to or greater than a height of the outermost edge of the central structure.

Abstract: A semiconductor device includes: a diffusion layer configuring a memory cell, and a diffusion layer configuring a dummy cell formed over the semiconductor substrate, interlayer insulating films formed over the semiconductor substrate, a cylinder layer insulating film including at least one concavity overlapping a diffusion layer and formed over an interlayer insulating film, a contact plug formed over one diffusion layer, a contact plug formed over another diffusion layer, a lower electrode formed over the side surfaces and bottom surface of the concavity and coupled to the diffusion layer by way of the contact plug, a dielectric material film formed over the lower electrode, over the cylinder layer insulating film and over the contact plug, and coupling by way of the contact plug to the diffusion layer, and an upper electrode formed over the inductive film material.

Abstract: A first first-conductivity-type diffusion layer, a first second-conductivity-type diffusion layer, a second first-conductivity-type diffusion layer, and a second second-conductivity-type diffusion layer are arranged in this order. In a region where the second second-conductivity-type diffusion layer and the first-conductivity-type layer are in contact with each other, impurity concentrations thereof are higher in a part in contact with a side face of the second second-conductivity-type diffusion layer than in a part at a bottom surface of the second second-conductivity-type diffusion layer.

Abstract: An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit. The third power supply voltage is intermediate between the first and second power supply voltages. The differential amplifier circuit includes, between the first and second power supplies, a differential input stage, first and second current mirror and first and second junction circuits. The output amplifier circuit includes first and second transistors connected between the first and third power supplies. The control circuit includes a third transistor connected between the output of the second current mirror and an end of the second junction circuit and supplied with a bias signal having a voltage in accordance with the third power supply voltage.

Abstract: A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode.

Abstract: A design method of a semiconductor device includes four steps. The first step is of arranging grid wiring which includes a plurality of wiring lines arranged in parallel to each other and a plurality of vias connecting the plurality of wiring lines with each other. The second step is of arranging a plurality of internal circuits connected to the grid wiring. The third step is of calculating a current density of a current flowing in the grid wiring by the plurality of internal circuits. The fourth step is of dividing each of the plurality of wiring lines into portions each having a wiring length such that electromigration corresponding to the current density is suppressed.

Abstract: An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.

Abstract: According to the present invention, there is provided an electrode structure which includes: a nitride semiconductor layer; an electrode provided over the nitride semiconductor layer; and an electrode protective film provided over the electrode, wherein the nitride semiconductor layer contains a metal nitride containing Nb, Hf or Zr as a constitutive element, the electrode has a portion having a metal oxide containing Ti or V as a constitutive element formed therein, and the electrode protective film covers at least a portion of the electrode, and contains a protective layer having Au or Pt as a constitutive element.

Abstract: A bipolar transistor of the invention has a second base region 116 which is formed in the surface layer of a deep well, placed between a first base region and a sinker, connected to the first base region, has an impurity concentration larger than that of the first base region, and has a depth shallower than that of the first base region; and a buried layer formed in a semiconductor layer, which has the top surface thereof brought into contact with the deep well and the sinker, and has an impurity concentration larger than that of the deep well.

Abstract: A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.

Abstract: A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x1 of 40% or below and the second porous layer has a pore density x2 of (x1+5) % or above.