Abstract: A silicon substrate is restrained from being warped. A substrate is formed by use of a silicon substrate. The substrate has a first surface and a second surface opposite to each other. A metal film is formed over the first surface. An interconnection layer is formed over the second surface. The metal film has a face centered cubic lattice structure. When the metal film is measured by XRD (X-ray diffraction), the [111] orientation intensity A(111), the [220] orientation intensity A(220) and the [311] orientation intensity A(311) of the metal film satisfy the following: A(111)/{A(220)+A(311)}?10.

Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

Abstract: A power-supply apparatus according to an aspect includes an inductor, a transistor that supplies, in an on-state, a current to the input side of the inductor, a second transistor that becomes, when the first transistor is in an off-state, an on-state and thereby brings the input side of the inductor to a predetermined potential, a signal generation unit that generates voltage signals corresponding to a current flowing to the inductor, an amplifier that outputs a current according to the voltage signals, a converter that converts the current output from the amplifier into a voltage signal, and a control unit that controls the transistors based on a first feedback signal corresponding to the voltage on the output side of the inductor and the voltage signal, which is used as a second feedback signal.

Abstract: A semiconductor device has a chip region including a back-side illumination type photoelectric conversion element, a mark-like appearance part, a pad electrode, and a coupling part. The mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed in a semiconductor substrate. The pad electrode is arranged at a position overlapping the mark-like appearance part. The coupling part couples the pad electrode and mark-like appearance part. At least a part of the pad electrode on the other main surface side of the substrate is exposed through an opening reaching the pad electrode from the other main surface side of the substrate. The mark-like appearance part and coupling part are arranged to at least partially surround the outer circumference of the opening in plan view.

Abstract: A semiconductor device includes a semiconductor chip including a main surface, an internal circuit including a plurality of transistors, formed on the main surface, a bonding pad electrically connected to the internal circuit, formed on the main surface, an inductor for communicating an external device in a non-contact manner, formed on the main surface, and a seal ring formed along an outer peripheral edge of the semiconductor chip to surround the internal circuit and the bonding pad in a plan view. The inductor has a configuration to surround the internal circuit and the bonding pad in the plan view and along the seal ring. The inductor is arranged inside the seal ring.

Abstract: The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply. The word line level fixing circuit includes multiple level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a fixed potential and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to turn-on of the second power supply.

Abstract: A semiconductor apparatus that can detect the amplitude level of harmonics is provided. A semiconductor apparatus includes a common mode detector circuit that detects alternating current (AC) signals in a common mode, and a detector circuit that detects the amplitude level of an even-order harmonic output from the common mode detector circuit. The common mode detector circuit combines the AC signals being differential signals in common mode, thereby cancelling out odd-order harmonics to obtain direct current and even-order harmonics. The detector circuit detects the amplitude level of the even-order harmonics from a signal obtained by the common mode detection, and outputs the detected amplitude level.

Abstract: Provided is a semiconductor device including: a memory cell array including a plurality of memory cells disposed in a matrix; and a peripheral circuit adjacent to the memory cell array. Each of the memory cells includes: a capacitive element including a lower electrode having a cylinder shape extending in a direction perpendicular to a principal surface of a substrate; and a switch transistor provided between the capacitive element and a bit line, turning on/off of the switch transistor being controlled based on a potential of a word line. The peripheral circuit includes a signal line that is adjacent to the lower electrode in a horizontal direction parallel to the principal surface and is supplied with a fixed potential, or a pair of signal lines respectively supplied with complementary potentials.

Abstract: To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.

Abstract: Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.

Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abstract: A semiconductor device includes a word line coupled to a mask ROM memory cell, a bit line pair coupled to the memory cell, a differential sense amplifier for amplifying the potential difference of the bit line pair, and a logic circuit for detecting whether the logic states of the bit line pair match or not. In this way, when there is a failure in the memory cell, it is possible to prevent the semiconductor device from passing the test as a result of the determination that the actual value is the same as the expected value in the test even if there is no potential difference in the bit line pair.

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

Abstract: A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor.

Abstract: When graphics computations are to be performed to calculate the display data of a figure to be drawn within a frame that is formed of a plurality of lines in accordance with input vector data, the present invention reduces the storage capacity of a RAM to which a work area for storing intermediate data is allocated. When the graphics computations are to be performed, the frame in which the figure is to be displayed is segmented into a plurality of drawing areas for each of the lines. As regards the work area for storing the intermediate data, the same work area is allocated to all the drawing areas. The graphics computations for calculating the intermediate data of the individual drawing areas are sequentially performed by repeatedly using the same work area.

Abstract: A semiconductor device includes a TSV that penetrates a silicon substrate. A seal ring is provided from a first low relative permittivity film that is closest to the silicon substrate to a second low relative permittivity film that is farthest from the silicon substrate. The seal ring is formed to surround the TSV in bird's eye view on the silicon substrate from a wafer front surface. This achieves suppression of generation or progress of a crack in a low relative permittivity film in a semiconductor device including the low relative permittivity film and a TSV.

Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p?-type polysilicon film with a high impurity concentration deposited thereon.

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract: Transistors and methods for fabricating the same include annealing channel portions of one or more semiconductor fins that are uncovered by a protective layer in a gaseous environment to reduce fin width, to produce a fin profile that is widest at the bottom and tapers toward the top, and to round corners of the one or more semiconductor fins.