Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.