Patents Assigned to ROHM Co., Ltd.
  • Patent number: 11885763
    Abstract: A gas concentration measurement system includes a limiting current-type gas sensor, a voltage source connected to the limiting current-type gas sensor, a current detector connected to the limiting current-type gas sensor, and a gas concentration arithmetic unit connected to the current detector. The voltage source supplies first and second voltages to the limiting current-type gas sensor. The first and second voltages generate first and second limiting currents corresponding to first and second gases, respectively, in the limiting current-type gas sensor. The current detector acquires first and second limiting current values of the limiting current-type gas sensor when the first and second voltages are applied to the limiting current-type gas sensor, respectively.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: January 30, 2024
    Assignee: ROHM Co., LTD.
    Inventors: Shunsuke Akasaka, Yurina Amamoto, Ken Nakahara
  • Patent number: 11885647
    Abstract: A sensor apparatus includes a resonator, a transducer, a damping resistor, a first switch, a filter stage, a second switch, and a noise rejection stage. The transducer is configured to detect a position of the resonator. The damping resistor is configured to electrostatically actuate the transducer and convert a thermomechanical noise of the resonator to an electromechanical noise. The first switch is configured to receive a first signal from the transducer. The filter stage is configured to receive the first signal and adjust a phase and a gain of the first signal and output a filtered first signal. The second switch is configured to receive a second signal from the transducer. The noise rejection stage is configured to receive the filtered first signal and the second signal and reduce the filtered first signal from an output signal.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: January 30, 2024
    Assignee: ROHM Co., Ltd.
    Inventor: Jonah Dewall
  • Patent number: 11888399
    Abstract: In a first mode, a first feedback controller generates a first control signal SCTRL1 based on a signal at a first feedback pin, so as to control a first pre-driver. A second feedback controller ¥ generates a second control signal based on a signal at a second feedback pin, so as to control a second pre-driver. In a second mode, the first feedback controller ¥ generates the first control signal based on a signal at the first feedback pin, so as to control the first pre-driver. The second pre-driver drives the second pre-driver based on a third control signal received from a first circuit block.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 30, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Kazunori Itou
  • Patent number: 11888058
    Abstract: The semiconductor device of the present invention includes a semiconductor layer which includes an active portion and a gate finger portion, an MIS transistor which is formed at the active portion and includes a gate trench as well as a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench at the gate finger portion, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region which is formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: January 30, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Publication number: 20240029925
    Abstract: A resistor includes a first insulator, a resistive body, a second insulator, a pair of electrodes, and a covering body. The first insulator has a first obverse surface facing in a thickness direction thereof. The resistive body is provided on the first obverse surface. The second insulator covers the resistive body. The pair of electrodes are electrically connected to the resistive body at both sides in a first direction perpendicular to the thickness direction. The covering body is formed on at least one of the first insulator and the second insulator. The covering body has electrical conductivity. The first layer is in contact with at least one of the first insulator and the second insulator.
    Type: Application
    Filed: October 6, 2023
    Publication date: January 25, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Kosaku TANAKA
  • Publication number: 20240030907
    Abstract: A semiconductor device includes a semiconductor chip which has a main surface and a main transistor which includes a first system transistor and a second system transistor that are each formed in the main surface so as to be individually controlled, in which the first system transistor includes a first composite cell which is constituted of an ?-number (??2) of first unit transistors that are arrayed so as to be mutually adjacent to the main surface and that each have a first trench structure including a first electrode embedded in a first trench formed in the main surface, and the second system transistor includes a second composite cell which is arranged so as to be adjacent to the first composite cell and constituted of a ?-number (??2) of second unit transistors that are arrayed so as to be mutually adjacent to the main surface and that each have a second trench structure including a second electrode embedded in a second trench formed in the main surface.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Applicant: ROHM CO., LTD.
    Inventors: Hajime OKUDA, Yoshinori FUKUDA, Yuji OSUMI
  • Publication number: 20240029949
    Abstract: An insulating transformer includes an insulation layer, a transformer embedded in the insulation layer, and a capacitor. The transformer includes first and second coils. The first coil includes a first signal terminal and a first ground terminal. The second coil is separated from the first coil in a thickness direction of the insulation layer and includes a second signal terminal and a second ground terminal. The capacitor includes first and second capacitor electrodes. The first capacitor electrode is connected to the first ground terminal of the first coil. The second capacitor electrode is located between the first capacitor electrode and the second coil and connected to the second ground terminal of the second coil. The insulating transformer further includes a first insulation film located between the first coil and the first capacitor electrode, and a second insulation film located between the second coil and the second capacitor electrode.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 25, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Bungo TANAKA
  • Publication number: 20240030336
    Abstract: A nitride semiconductor device includes: an electron transport layer constituted by a nitride semiconductor; an electron supply layer formed on the electron transport layer and constituted by a nitride semiconductor that has a larger band gap than the electron transport layer; a gate layer formed on the electron supply layer and constituted by a nitride semiconductor that has a smaller band gap than the electron supply layer and includes an acceptor impurity; a gate electrode formed on the gate layer; and a drain electrode and a source electrode in contact with the electron supply layer. The acceptor impurity includes zinc and magnesium, and the concentration profile of the zinc in the thickness direction of the gate layer is different from the concentration profile of the magnesium in the thickness direction of the gate layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: January 25, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Norikazu ITO
  • Publication number: 20240030303
    Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.
    Type: Application
    Filed: October 5, 2023
    Publication date: January 25, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Yuki NAKANO
  • Publication number: 20240030276
    Abstract: An isolator includes an insulation layer and a capacitor embedded in the insulation layer. The capacitor includes: a first electrode portion arranged in the insulation layer and connected to a first pad; a second electrode portion arranged in the insulation layer and connected to a second pad; and an intermediate electrode portion arranged in the insulation layer and not connected to the first electrode portion and the second electrode portion. The intermediate electrode portion includes a first intermediate layer, a second intermediate layer, and a connector connecting the first intermediate layer and the second intermediate layer. The capacitor is formed by coupling the first electrode portion and the second electrode portion through the intermediate electrode portion.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Applicant: ROHM CO., LTD.
    Inventors: Keiji WADA, Yasushi HAMAZAWA
  • Publication number: 20240030333
    Abstract: A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer, a gate electrode, a passivation layer, a source electrode, and a drain electrode. The gate layer includes a ridge including an upper surface of the gate layer, a source-side extension smaller in thickness than the ridge, and a drain-side extension smaller in thickness than the ridge. The source-side extension includes a first step portion including an upper surface parallel to a bottom surface of the gate layer and a first intermediate portion connecting the first step portion to the ridge. The drain-side extension includes a second step portion including an upper surface parallel to the bottom surface of the gate layer and a second intermediate portion connecting the second step portion to the ridge. The first intermediate portion has a cross-sectional area that is greater than that of the second intermediate portion.
    Type: Application
    Filed: July 12, 2023
    Publication date: January 25, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Kazuya NAGASE
  • Patent number: 11881863
    Abstract: A comparator circuit includes a first comparator configured to compare a voltage based on an input voltage with a first reference voltage, a charge/discharge portion configured to switch between charging and discharging of a capacitor based on an output of the first comparator, a second comparator configured to compare a voltage of the capacitor with a second reference voltage, and a control portion. The control portion is configured to, in a case where the voltage of the capacitor is larger than a predetermined value when the charge/discharge portion performs switching from the charging of the capacitor to the discharging thereof, supply a predetermined voltage instead of the voltage based on the input voltage to the first comparator until the voltage of the capacitor becomes smaller than the predetermined value so that the discharging of the capacitor is maintained by the charge/discharge portion.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: January 23, 2024
    Assignee: Rohm Co., Ltd.
    Inventor: Makoto Yasusaka
  • Patent number: 11880254
    Abstract: A power supply system of the present disclosure includes: a plurality of output terminals, configured to output an output voltage; a group setting circuit, configured to group the plurality of output terminals; an anomaly detection circuit, configured to detect anomaly; and a control circuit, configured to stop an output from the output terminals belonging to groups in which an anomaly is detected by the anomaly detection circuit, and maintain an output from the output terminals belonging to groups in which an anomaly is not detected by the anomaly detection circuit.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: January 23, 2024
    Assignee: Rohm Co., Ltd.
    Inventor: Takumi Yamada
  • Patent number: 11881479
    Abstract: The present invention provides a nitride semiconductor device, including an insulating substrate, a substrate over the first surface of the insulating substrate, a first lateral transistor over a first region of the substrate, wherein the first lateral transistor includes a first nitride semiconductor layer formed over the substrate, and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer, and a second lateral transistor over a second region of the substrate, wherein the second lateral transistor includes a second nitride semiconductor layer formed over the substrate, and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer, and a separation trench formed over a third region, wherein the third region is between the first region and the second region.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: January 23, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Hirotaka Otake
  • Publication number: 20240017989
    Abstract: A MEMS device includes a substrate which has a first main surface and a second main surface facing the first main surface, and in which a silicon substrate, a silicon carbide layer having conductivity, and a silicon layer are sequentially stacked from a second main surface side toward a first main surface side, a cavity recessed over the silicon layer, the silicon carbide layer, and the silicon substrate from the first main surface of the substrate to the second main surface side of the substrate, a MEMS electrode which is arranged in the cavity, is composed of the silicon layer and the silicon carbide layer, and is spaced apart from a bottom surface of the cavity to the first main surface side, and an isolation joint which divides the MEMS electrode in a plan view and mechanically connects and electrically isolates both sides of the divided MEMS electrode.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 18, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Martin Wilfried HELLER
  • Publication number: 20240022246
    Abstract: An isolation transformer includes an insulation layer and a transformer. The transformer includes a first coil and a second coil embedded in the insulation layer. The first coil and the second coil are opposed to each other in a thickness-wise direction of the insulation layer. The first coil and the second coil include non-overlapping portions that do not overlap each other in the thickness-wise direction of the insulation layer.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Applicant: ROHM CO., LTD.
    Inventors: Keiji WADA, Yasushi HAMAZAWA
  • Publication number: 20240021598
    Abstract: This isolation transformer includes: an isolation layer; a transformer having a first coil and a second coil; and a capacitor having a first capacitor electrode and a second capacitor electrode disposed between the first coil and the second coil. The isolation layer includes a first isolation film in which the first coil is embedded, a second isolation film on the upper surface of the first isolation film, a protective film on the upper surface of the second isolation film, a third isolation film on the upper surface of the protective film, a fourth isolation film on the upper surface of the third isolation film, and a fifth isolation film on the upper surface of the fourth isolation film. The second capacitor electrode is formed between the third isolation film and the fourth isolation film. The second coil is formed between the fourth isolation film and the fifth isolation film.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 18, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Bungo TANAKA
  • Publication number: 20240021599
    Abstract: An isolation transformer includes an insulation layer, a transformer, and a capacitor. The transformer includes first and second coils separated from each other in a thickness-wise direction of the insulation layer. The capacitor includes a first capacitor electrode and a second capacitor electrode. The insulation layer includes thin films and interlayer insulation films alternately stacked in the direction. The thin films include first and second thin films separated from each other in the direction. The interlayer insulation films include a first interlayer insulation film located next to the first thin film in the direction and a second interlayer insulation film located next to the second thin film in the direction. The first capacitor electrode is formed between the first thin film and the first interlayer insulation film. The second capacitor electrode is formed between the second thin film and the second interlayer insulation film.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Applicant: ROHM CO., LTD.
    Inventor: Bungo TANAKA
  • Patent number: D1012048
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: January 23, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Yoshihisa Tsukamoto, Akihiro Kimura, Masaaki Matsuo
  • Patent number: D1012049
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: January 23, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Yoshihisa Tsukamoto