Abstract: When a level of an asynchronous internal clock enabling signal asynchronous with an external clock signal is risen just after or just before a level change of the external clock signal, a for-synchronization-circuit enabling signal synchronized with the external clock signal is produced in a control signal producing circuit on condition that a level of the for-synchronization-circuit enabling signal is risen at a time which is later than the level change of the external clock signal by two clocks of the external clock signal. Therefore, a reset time-period from the level change of the external clock signal to the level change of the for-synchronization-circuit enabling signal, is obtained. A synchronization circuit is reset in the reset time-period according to the external clock signal and the asynchronous internal clock enabling signal, and, a test signal is produced in the synchronization circuit from the for-synchronization-circuit enabling signal after the reset time-period passes.

Abstract: A radio-frequency power supply (1) and a matching box (2) are electrically connected with a coaxial cable (4) while the matching box (2) and a main unit (3) are electrically connected with a coaxial cable (5). Around the coaxial cable (5), a radio-frequency current transformer (6) is provided and an output signal from the radio-frequency current transformer (6) is given to an oscilloscope (7). In an apparatus using the radio-frequency power supply, with this constitution, a method for measuring a radio-frequency current can be provided, by which spurious components and frequency variation of the radio-frequency current can be measured simply and precisely at a low cost, without changing a series of communication paths, such as the coaxial cable, for the radio-frequency current.

Abstract: There is described a mask inspection system suitable for reliably removing dust particles from a mask. The system is intended for eliminating the necessity of repetition of dust particle inspection by simultaneous removal of dust particles and checking of the same. When dust particles are detected on a mask, the dust particles are removed. A gas blowing device and a dust particle suction device are disposed in positions where they face the mask. The gas blowing device squirts high-pressure gas to the dust particles from above, and the dust particle suction device sucks the dust particles from blow. A particle counter is connected to the dust particle suction device. When the particle counter counts the number of dust particles, the dust particles are determined to be removed from the mask.

Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.

Abstract: The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to an improvement for enhancing a gate breakdown voltage. In order to achieve the object, gate wirings (9), (10) and (13) are provided to keep away from an upper end (UE) of an edge of a gate trench (6) along its longitudinal direction. More specifically, the gate wiring (9) coupled integrally with an upper surface of a gate electrode (7) is formed apart from the upper end (UE) and the gate wiring (10) is formed on an insulating film (4) also apart from the upper end (UE). The two gate wirings (9) and (10) are connected to each other through the gate wiring (13) formed on a BPSG layer (11). Moreover, an upper face of the gate electrode (7) is positioned on the same level as an upper main surface of a semiconductor substrate (90) or therebelow in the vicinity of the upper end (UE).

Abstract: A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.

Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.

Abstract: A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.

Abstract: An IC tester includes a test pattern storage circuit that stores a test pattern, a delay amount storage table that stores a test condition, an offset address generation circuit that divides the delay amount storage table into a plurality of regions and selects a region from the plurality of divided regions, a reference signal delay circuit that delays a reference signal according to a test condition stored in a region of the delay amount storage table selected by the offset address generation circuit, and a test waveform formation circuit that generates a test waveform according to the test pattern stored in the test pattern storage circuit and the reference signal delayed by the reference signal delay circuit.

Abstract: A prober can make an appropriate evaluation in a microcurrent region. A wafer (9) is disposed on a chuck (8) in a casing (1). In the upper surface of the chuck (8), an electrode (8a) is formed which is connected to a power supply (11) via a wire (10). In the casing (1), a cylindrical electromagnetic shielding box (7) is disposed with the upper surface open. The upper surface of the casing (1) and the side surfaces and bottom surface of the electromagnetic shielding box (7) form a closed space (30) for surrounding the chuck (8) and the wafer (9). Also, a loader (6) for driving the chuck (8) and the electromagnetic shielding box (7) is disposed in the casing (1). On the upper surface of the casing (1), a tester head (3) is disposed with a probe card (4) disposed therein. Since part of the upper surface of the casing (1) is open, probe needles (5) of the probe card (4) protrude into the casing (1) through the opening.

Abstract: Reaction products due to etching of a semiconductor sample by using a reactive gas are removed by using a liquid chemical that contains sulfuric acid and hydrofluoric acid at a volume mixing ratio of (5 to 7):(1/400 to 1/1000) and is kept at 25.degree.-70.degree. C. Reaction products and a resist mask are removed simultaneously by using a liquid chemical that contains sulfuric acid, a hydrogen peroxide solution, and hydrofluoric acid at a volume mixing ratio of (5 to 7):1:(1/400 to 1/1000) and is kept at 70.degree.-100.degree. C.

Abstract: A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6).

Abstract: A drying apparatus and method of drying is provided for drying a semiconductor member mounted in a carrier that is placed in a processing tank through contact with isopropyl alcohol. An isopropyl alcohol liquid is vaporized in a bottom portion of the processing tank, and the resulting vapor is condensed in its top portion. A heater is disposed so as to heat the inside of the processing tank to keep the inside at a predetermined temperature range in a middle-layer portion, i.e., a drying portion, of the processing tank. The heater is covered with a heat insulating member.

Abstract: The present invention is directed to providing an apparatus which is improved so as to remove a contamination on a substrate efficiently. This apparatus includes a jet nozzle jetting out droplets toward a substrate. A liquid supply device and a gas supply device are connected to the jet nozzle. A mixing device mixing a liquid and a gas supplied to the jet nozzle and changing the liquid into the droplets is provided in the jet nozzle.

Abstract: A semiconductor device allowing the manufacturing process to be simplified and fine structures therein to be readily formed and a manufacturing method thereof are provided. In the semiconductor device, a conductive layer is used as a mask during etching for forming a first opening.

Abstract: When an IPA is fed to a nozzle, a flow of the IPA passing through holes is generated. The flow becomes film-shaped and goes downward along an inner surface of a side wall of a processing vessel. Then, the flow is collected by a liquid receiving section formed in a lower portion of the processing vessel and discharged to an outside. The inner surface of the side wall of the processing vessel is covered with the flow of the IPA. Therefore, an IPA vapor can be prevented from condensing uselessly on the inner surface. As a result, the IPA vapor is effectively utilized for condensation on a surface of the object to be processed which is mounted on a pan. Thus, the defective dryness of the object can be prevented.

Abstract: A method of manufacturing a semiconductor device can suppress an etching damage to a bipolar transistor part and a CMOS transistor part while simplifying a manufacturing process. According to this manufacturing method, an external base leader electrode layer which will form an external base leader electrode is used as an etching protection film for forming a CMOS transistor, and a layered film including a polycrystalline silicon film which will ultimately form a gate electrode is used as an etching protection film during formation of a bipolar transistor. Thereby, a step of forming the etching protection film can be utilized also as a step of forming the external base electrode and the gate electrode. Consequently, the etching damages to the bipolar transistor part and the CMOS transistor part are suppressed while simplifying the manufacturing process.

Abstract: A method comprises steps of: forming a FBM (step S1); generating a second failure map by compressing data of the FBM (step S2); recognizing a failure mode from the second failure map (step S3); selecting a specific failure mode (step S4); and analyzing the specific failure mode by using a part of the corresponding FBM (step S5). This makes a detail analysis possible while suppressing the number of processing data, and thereby achieves a failure analysis method and device improving accuracy and reliability in comparison result.

Abstract: Data containing defect position coordinates obtained based on the result of physical inspection of foreign material, a defect or the like at the surface of a semiconductor wafer by a defect inspecting apparatus is stored. Also stored is data of physical coordinates obtained based on fail bit data from a tester. Data indicating an additional failure region is produced by an additional failure region estimating apparatus based on the fail bit data, and is stored. Collation produces data of corrected physical position coordinates by adding the stored data of limitation by failure mode to the stored data of physical position coordinates, and collates the data of corrected physical position coordinates with stored data of defect position coordinates. Accordingly, accuracy in collation is improved, and failure can be analyzed even if caused not by a defect located at an address of the failure obtained by the fail bit data but by a defect relating to the defect located at the address of a failure.

Abstract: The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.