Abstract: An analog-to-digital conversion device according to one or more embodiments independently executes each of events instructed by a host device. Each of two or more analog-to-digital converters include an execution control unit, an event management unit that notifies of a synchronization instruction when a synchronous conversion event set up with a synchronous conversion operation is instructed as the event, and an operation control unit.

Abstract: Semiconductor base including: silicon-based substrate; buffer layer including first and second layers alternately on silicon-based substrate, first layer made of nitride-based compound semiconductor containing first material, second layer made of nitride-based compound semiconductor containing second material having larger lattice constant than first material; channel layer on buffer layer and made of nitride-based compound semiconductor containing second material, buffer layer has: first composition graded layer between at least one of first layers and second layer immediately thereabove, made of nitride-based compound semiconductor whose composition ratio of second material is increased gradually upward, whose composition ratio of first material is decreased gradually upward; second composition graded layer between at least one of second layers and first layer immediately thereabove, made of nitride-based compound semiconductor whose first material is increased gradually upward, whose composition ratio of s

Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.

Abstract: A device and method for calculating switching time. The device includes: a digital calculator configured to calculate a next on time according to an output voltage signal and an inductor current signal detected during an on period of a switching element and calculate a next off time according to the next on time, an input voltage signal and the output voltage signal; and a signal generator configured to generate a pulse width modulation signal for controlling the switching element, according to the next on time and the next off time. Therefore, a digital controlling manner is provided, not only the number of components and the cost are decreased, but also detection accuracy is improved with a simple structure.

Abstract: A microcontroller unit includes: a first arithmetic processing unit, which is able to access a data bus; a second arithmetic processing unit, which includes a processor capable of accessing the data bus, and a memory. The microcontroller unit performs a data transmitting process between peripheral circuits connected to the data bus; a first arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the data bus; and a second arbitration circuit, which is embedded in the second arithmetic processing unit and arbitrates access to the memory. The memory stores arithmetic processing sequences in association with event signals transmitted from the peripheral circuits, and in response to input of the event signals, the processor executes the arithmetic processing sequences corresponding to the event signals.

Abstract: A semiconductor device in embodiments, may include a device region having: two active trenches, each having at least a gate electrode. Two insulated trenches each having an electrode may be formed between the two active trenches separated by a junction. First p-doped layers may be provided between a first active trench and a first insulated trench, and between a second active trenches and a second insulated trench. Second p-doped layers may be provided between a first insulated trench and a second insulated trench with the junction arranged therebetween. The second p-doped layers may be provided on an external surface of the respective first one and second one of the two insulated trenches at a depth and a thickness set to form a current path when the power semiconductor device is in an OFF state.

Abstract: A semiconductor device includes: a semiconductor base; a trench insulating film 50 which is provided on the inner wall surface of a trench formed from the upper surface of the semiconductor base in the film thickness direction and includes a charged region which is charged positively; and a gate electrode 80 provided on the trench insulating film 50 within the trench. The positive charge density of the charged region at least in a side part of an outer region of the trench insulating film 50 which is provided on the side surface of the trench is higher than that of an inner region of the trench insulating film which is opposite to the outer region, the outer region being in contact with the semiconductor base.

Abstract: A substrate for semiconductor device includes a substrate, a buffer layer which is provided on the substrate and made of a nitride semiconductor, and a device active layer which is provided on the buffer layer and composed of a nitride semiconductor layer, wherein the buffer layer contains carbon and iron, a carbon concentration of an upper surface of the buffer layer is higher than a carbon concentration of a lower surface of the buffer layer, and an iron concentration of the upper surface of the buffer layer is lower than an iron concentration of the lower surface of the buffer layer. As a result, the substrate for semiconductor device can reduce a leak current in a lateral direction at the time of a high-temperature operation while suppressing a leak current in a longitudinal direction.

Abstract: A current collapse characteristic is sufficiently suppressed. After forming a large opening (first opening) passing through both of a TEOS oxide layer 42 and an oxide layer 41, a thin oxide layer (third insulating layer) 43 entirely covering the layers and the opening. In the oxide layer 43 inside the first opening, an opening (second opening) for exposing a group-III nitride semiconductor layer 10 is provided. A gate electrode 50 is formed at a slanted portion of the first opening including the second opening. A taper angle of the opening is smaller in the TEOS oxide layer 42 than in the oxide layer 41.

Abstract: Provided is a low cost semiconductor device in which occurrence of chipping and a crack during dicing is suppressed. A nitride layer (silicon nitride layer) 23 is formed on an oxide layer 22. In FIG. 1, a thick organic layer 24 is formed as a top layer. The semiconductor device 1 is characterized by its structure on a side of its end portion. In FIG. 1, the end portion E of the semiconductor device 1 is formed by cutting with a blade in the vertical direction during dicing. An edge E1 of both the oxide layer 22 and the nitride layer is located apart from an edge of a semiconductor substrate 10. An edge E2 of the organic layer 24 on the nitride layer 23 is located inside the edge E1 of the nitride layer 23 (on a side more distant from the edge E).

Abstract: A semiconductor device and a method for forming the semiconductor device. The semiconductor device includes: a unipolar component at least including an epitaxial layer; a transition layer connected to the epitaxial layer; and a bypass component connected to the transition layer; the unipolar component and the bypass component are connected in parallel and the transition layer is configured between the unipolar component and the bypass component.

Abstract: A semiconductor device and a method for forming the semiconductor device. The semiconductor device includes: a unipolar component at least including a first epitaxial layer and a first substrate; and a bypass component at least including a second epitaxial layer and a second substrate; the unipolar component and the bypass component are connected in parallel; a difference of a thickness of the unipolar component and a thickness of the bypass component is lower than or equal to a predetermined value.

Abstract: A semiconductor base substance includes: a substrate; a buffer layer which is made of a nitride semiconductor and provided on the substrate; and a channel layer which is made of a nitride semiconductor and provided on the buffer layer, wherein the buffer layer includes: a first region which is provided on the substrate side and has boron concentration higher than acceptor element concentration; and a second region which is provided on the first region, and has boron concentration lower than that in the first region and acceptor element concentration higher than that in the first region. As a result, the semiconductor base substance which can obtain a high pit suppression effect while maintaining a high longitudinal breakdown voltage is provided.

Abstract: A data processing device according to one or more embodiment is disclosed. The data processing device may include a first power-on reset circuit that generates a first power-on reset signal depending on power source voltage, and a processor that activates based on a first power-on reset signal generated by the first power-on reset circuit and that runs software. The processor determines if the normal first power-on reset signal is used to cause the processor to activate and run the software.

Abstract: A device and method for controlling a power converter. The device includes an activation terminal configured to obtain a first voltage based on the input voltage; a controlling terminal configured to obtain a second voltage based on the output voltage; and a digital controller configured to obtain a driving power based on the first voltage and/or the second voltage; the digital controller is configured to obtain the driving power at least based on the first voltage when the power converter is stopped. Therefore, a sufficient driving power can be provided for the digital controller even when the power converter is stopped.

Abstract: A power conversion device according to one or more embodiments may include: a microcomputer; and an output circuit controlled by the microcomputer, including an output unit that converts an input power into a predetermined power and outputs the predetermined power, an internal power source that supplies a power source to the microcomputer, a driver that drives the output unit by a signal from the microcomputer, and a microcomputer stop transition unit that, when an operation of the power conversion device is stopped, outputs a microcomputer stop signal to the microcomputer and causes an operation of the microcomputer to transition to a stop state. In one or more embodiments, after the microcomputer stop transition unit causes the operation of the microcomputer to transition to a stop state, the microcomputer or the output circuit may stop an output of the internal power source.

Abstract: A device and method for controlling a power supply. The method includes: a voltage signal in a primary winding is delayed, and the delayed voltage signal is sampled and held after a time when a rectifying diode stops conducting a current, then the sampled and held signal is used as a feedback signal of the power supply. Therefore, only one sampling and holding circuit is needed, the area of the circuit can be reduced and the cost of the integrated circuit can be decreased, meanwhile regulation characteristics are not deteriorated.

Abstract: A semiconductor wafer and a method for forming a semiconductor. The semiconductor wafer includes: a first semiconductor component having a first device; a second semiconductor component having a second device; an insulation layer laterally extending to the first semiconductor component and the second semiconductor component; and a grind layer configured on or adjacent to a backside of the semiconductor wafer. Therefore, chipping or cracking can be decreased or avoided when the grind layer is exposed during the thinning process (such as backside grinding).

Abstract: A device and method for controlling a power supply. The method includes: a first correction signal is generated according to a down-slope waveform and a second correction signal is generated according to an up-slope waveform, in a period of the switching element. Therefore, two kinds of corrections can be performed by using an oscillator, while the area of the circuit can be reduced and the cost of the integrated circuit can be decreased.

Abstract: A power conversion device according to one or more embodiments may include: a microcomputer; and an output circuit controlled by the microcomputer, including an output unit that converts an input power into a predetermined power and outputs the predetermined power, an internal power source that supplies a power source to the microcomputer, a driver that drives the output unit by a signal from the microcomputer, and a microcomputer stop transition unit that, when an operation of the power conversion device is stopped, outputs a microcomputer stop signal to the microcomputer and causes an operation of the microcomputer to transition to a stop state. In one or more embodiments, after the microcomputer stop transition unit causes the operation of the microcomputer to transition to a stop state, the microcomputer or the output circuit may stop an output of the internal power source.