Abstract: A Device Under Test ("DUT") is monitored to determine when a test stops due to failure, completion, or otherwise. A series of signal stimulus in the form of a maintain active signal are applied to the DUT after the test has stopped. This protects devices that need continuous functional stimulus while connected to a power source. Upon the resumption of the test, the maintain active signal stimulus is synchronously replaced with an input test signal stimulus.

Abstract: A number of local sequencers, one for each pin of the device under test is disclosed. Each local sequencer is provided with a global clock, a global time zero signal indicating the clock edge for referencing the start of a test, and a period vernier indicating an offset from the clock for the start of the test period. Each local sequencer uses this information to generate its own test events referenced to the test period with individual calibration delays factored in locally. Each local sequencer is individually programmable so that different sequencers can provide different numbers of events during the same test period.

Abstract: Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit.

Abstract: A plurality of "pin slice" circuits, each associated with a separate pin of the device under test (DUT). Each pin slice circuit contains its own memory and registers and circuitry for generating the necessary test signals. Test data is loaded into the individual pin slice circuits in a vertical word fashion, such that all of the bits of the vertical word correspond to the individual pin, allowing the characteristics of an individual pin test sequence to be varied independently of the other pins. A participate memory is used to select different groupings of the pin slice circuits which are to be programmed in parallel when a group of pins are to receive the same test signals. Separate enable signals to the various stages of the pin slice circuits allow different aspects of the test pattern to be also varied independently.

Abstract: Driver circuits are provided which also serve as termination and clamp in an IC tester. When it is to drive a port of a device under test (DUT) between two predetermined voltage levels, the driver's I/O terminal is switched between two predetermined voltage levels with an output impedance that matches the transmission line between the driver circuit and the DUT. When the DUT's port is supplying an output signal, the driver circuit can be programmed to provide one of two types of termination. If the DUT's port is specified as capable of driving the load, the transmission line between the driver circuit and the DUT is terminated by switching the driver circuit's I/O terminal to a predetermined voltage level with an impedance of Z.sub.0. If the DUT's port is not specified as being capable of driving such a termination load, the driver circuit functions like a Z-clamp circuit.

Abstract: Parking machines communicate automatically with service personnel located at a central station in response to the occurrence of a machine error. The service personnel are thus made aware promptly of this situation without having to travel to the site of each parking machine so that appropriate action can be timely taken. The parking machine stores an error signal, and the telephone number of the central station is then dialed. When a communication link is established telephonically, an audible message is generated by the parking machine and transmitted to the central station identifying the parking machine and a machine error. As long as the machine is not serviced, it will re-dial the central station to transmit the error message, and this is repeated at a time interval set according to whether the error has disabled the parking machine or not.

Abstract: Focused ion bean (FIB) milling through a power plane of a device to expose or cut a hidden, lower-layer conductor requires accurate positioning relative to the hidden conductor of a box defining boundaries of the FIB operation. This can in general be done by aligning surface information (topology or voltage contrast) visible in a FIB or scanning electron microscope (SEM) image with an overlay image generated from stored data describing the device. The location of the hidden conductor relative to the visible surface information is determined from the stored data. Advanced integrated circuits often do not provide enough unique surface information near the FIB operation area to align the images with sufficient accuracy.

Abstract: Electro-optical in-circuit testing, especially of large circuits such as those assembled on printed circuit boards, is achieved in an automatic test system by disposing an electro-optical sensor in proximity to the circuit conductors, applying test signals to the circuit under test, and measuring an optical property of the sensor at selected regions thereof corresponding to internal nodes, i.e. test points, of the circuit. The sensor may be an optical probe comprising a lens and a layer of electro-optical material which is adapted to be applied to the circuit. The electro-optical material may be either a polymer film or a crystal, the latter requiring a flexible coupling medium on the face applied to the circuit under test. The electro-optical material is provided with a reflective coating on one surface to facilitate a polarimetric measurement made transverse to the plane of the material.

Abstract: Methods and apparatus are disclosed for positioning the field of view in a system for IC probing or repair, where the system comprises means for supporting an IC device having multiple physical layers and multiple internal nets, and controllable positioning means for positioning the field of view relative to the device. A data set is prepared which describes each physical layer of the device as a plurality of reduced polygons. Each of the reduced polygons is associated with a physical layer of the device and with at least one net of the device. For each of a plurality of selected nets, polygons associated with the net are dilated to define the periphery of a region encompassed by the field of view when a point within the field of view is traced around the periphery of a reduced polygon. A bit plane of the dilated polygons is mapped for each net, and regions of overlap the mapped bit planes are identified.

Abstract: Focused ion beam (FIB) systems are used for IC mask or reticle repair and imaging and other applications. The impinging ions can cause an undesirable charge build-up on the specimen. Prior to beginning repair operations in a FIB system, a fluid containing a conductive material such as dimethyl ammonium salt is applied to the reticle, mask or device and allowed to dry, leaving a thin conductive layer on the specimen. A leakage path is preferably provided from the thin conductive layer to ground, to prevent charge buildup on the specimen. The FIB is used to cut through the conductive layer before commencing FIB deposition, to assure proper bonding of the deposited material. The technique also has application with electron beam imaging systems.

Abstract: By measuring the waveform of the reflected wave obtained by transmitting a pulse to an open-ended transmission line, a transfer function of the transmission line with respect to the incident wave is computed as a result of the measurement. Then, the waveform of the output wave at the output end or the open end of the transmission line is estimated in response to an individual input signal by using the transfer function computed. The transmission delay time of the transmission line is obtained by computing the time difference between the transient timing of the estimated waveform of the output wave and the transient timing of the waveform of the input signal.

Abstract: A method and apparatus for performing kinematic analysis of linkages using generalized mechanisms selected from a catalog of mechanisms. From an initial selection of mechanisms, the one most closely matching a desired behavior is chosen and an optimization procedure is conducted. The method may be preceded by a qualitative kinematic analysis or the qualitative analysis may be used in lieu of a catalog selection. An improved optimization technique and a closed form kinematic analysis method is described.

Abstract: Electro-optical in-circuit testing, especially of large circuits such as those assembled on printed circuit boards, is achieved in an automatic test system by disposing an electro-optical sensor in proximity to the circuit conductors, applying test signals to the circuit under test, and measuring an optical property of the sensor at selected regions thereof corresponding to internal nodes, i.e. test points, of the circuit. The sensor may be an optical probe, having a lens and a layer of electro-optical material which is adapted to be applied to the circuit. The electro-optical material may be either a polymer film or a crystal, the latter requiring a flexible coupling medium on the face applied to the circuit under test. The electro-optical material is provided with a reflective coating on one surface to facilitate a polarimetric measurement made transverse to the plane of the material.

Abstract: A method and apparatus for performing kinematic analysis of linkages is disclosed. Generalized mechanisms are selected from a catalog of mechanisms. From an initial selection of mechanisms, the one most closely matching a desired behavior is chosen and an optimization procedure is conducted. The method may be preceded by a qualitative kinematic analysis or the qualitative analysis may be used in lieu of a catalog selection. An improved optimization technique is disclosed, along with a closed form kinematic analysis method.

Abstract: An ATE system uses a single digital to analog converter and a single analog line for defining the reference voltage levels of a plurality of pin drivers and pin sensors. An advantage of using a single DAC is that the number of components for routing the reference voltage signals is reduced. Digital values for each high and low reference voltage level for each pin driver and each pin sensor are stored in memory. Such memory is addressed sequentially reference value by reference value, converted to analog format and routed along one common analog wire to a plurality of sample and hold circuits. The plurality of sample and hold circuits receive a pin driver/sensor address and the common analog signal. The address enables one of the plurality of sample and hold circuits and selects only one output line of the enabled sample and hold circuit. Such output line is coupled to a given reference terminal (e.g., reference high or reference low) of a given pin driver or a given pin sensor.

Abstract: A plurality of "pin slice" circuits, each associated with a separate pin of the device under test (DUT). Each pin slice circuit contains its own memory and registers and circuitry for generating the necessary test signals. Test data is loaded into the individual pin slice circuits in a vertical word fashion, such that all of the bits of the vertical word correspond to the individual pin, allowing the characteristics of an individual pin test sequence to be varied independently of the other pins. A participate memory is used to select different groupings of the pin slice circuits which are to be programmed in parallel when a group of pins are to receive the same test signals. Separate enable signals to the various stages of the pin slice circuits allow different aspects of the test pattern to be also varied independently.

Abstract: A modular ATE system includes a plurality of test modules and a receiver for use with a variety of fixtures to which printed circuit boards are to be coupled. Each test module includes a plurality of pin cards controlled by a single module controller. Multiple test module are included for testing a variety of functions. Test signals are generated by discrete sets of pin cards and controllers, then output to the receiver for interconnection to a fixture and printed circuit board(s) under test. A substantially wireless receiver is provided, including a translation board for electrically coupling test module pin cards to the fixture. By eliminating wiring and cabling by using a prefabricated translation board, noise is substantially reduced and test signal quality improved. The translation board defines prescribed signal mapping for interconnecting the I/O pins of ATE pin cards to the underside of the fixture. Different translation boards may have different mappings.

Abstract: A number of local sequencers, one for each pin of the device under test is disclosed. Each local sequencer is provided with a global clock, a global time zero signal indicating the clock edge for referencing the start of a test, and a period vernier indicating an offset from the clock for the start of the test period. Each local sequencer uses this information to generate its own test events referenced to the test period with individual calibration delays factored in locally. Each local sequencer is individually programmable so that different sequencers can provide different numbers of events during the same test period.

Abstract: A surface is probed with a pulsed electron beam and secondary electrons are detected to produce a detector signal. First portions of the detector signal are substantially dependent on the voltage of the surface being probed, while second portions of the detector signal are substantially independent of the voltage of the surface being probed. In general, the first and second portions of the detector signal include unwanted noise caused by low-level sampling due to beam leakage and/or by scintillator afterglow in the secondary-electron detector. The detector signal is sampled during the first signal portions and is sampled during the second signal portions. The sampled first signal portions are combined with the complement of the sampled second signal portions to produce a measured voltage signal representing voltage of the conductor. In a preferred sampling scheme, alternate electron-beam sampling pulses are held-off.

Abstract: A method and apparatus for simultaneously correlating a mask to a series of shifted positions of an image. A series of bits from a field representing an image are supplied to a number of buffer registers. A number of overlapping combinations of bits from the buffer registers are simultaneously compared with the mask bits and a signal is produced indicating the results of such comparison for each of the image bit combinations. Algebraic functions are applied to the separate combinations to relate individual comparisons. A statistical analysis is performed to determine a best fit of an image to a mask.