Abstract: In a data storage system with distributed data storage units, initialization-less parity can be practiced with a storage controller connected to a storage memory and multiple data storage units. Data locations of data storage devices of the respective data storage units can be arranged as distributed data storage groups as directed by the storage controller prior to receiving a write request to a distributed data storage group. Unwritten data locations of the distributed data storage group are identified by consulting the storage memory and each unwritten data storage location may be assumed to have a zero value when computing parity data for the distributed data storage group.

Abstract: Method and apparatus for managing data in a data storage device configured as a storage compute appliance. In some embodiments, the data storage device has a non-volatile memory (NVM) and a controller circuit. The NVM stores a plurality of data sets encrypted by at least one encryption key. The controller circuit performs a storage compute appliance process by locally decrypting the plurality of data sets in a local memory of the data storage device, generating summary results data from the decrypted data sets, and transferring the summary results data across the host interface to an authorized user without a corresponding transfer of any portion of the decrypted data sets across the host interface.

Abstract: Apparatus and method for transferring data between a processing circuit and a memory. In some embodiments, a data storage device has a main non-volatile memory (NVM) configured to store user data from a host device. A controller circuit is configured to direct transfers of the user data between the NVM and the host device. The controller circuit has a programmable processor and a secure data transfer circuit. The secure data transfer circuit executes memory access operations to transfer user data and control values between the processor and a local memory. A memory access operation includes receiving bits of a multi-bit control value on a multi-line bus from the processor, and activating a programmable switching circuit to randomly interconnect different ones of the multi-line bus to transpose the bits in the control value.

Abstract: A system includes a drawer and a fan assembly. The drawer includes a mounting structure with a support surface and an aperture. The fan assembly extends through the aperture and includes a fan module and a top cover. The top cover is coupled to the support surface.

Abstract: An electronic device which includes a cover, a base coupled to the cover to create an enclosure, a conductive layer positioned between the cover and the base and arranged to reduce radiation from entering the enclosure, and a gasket positioned between the cover and the base to create a seal and positioned between the conductive layer and the enclosure.

Abstract: A system may consist of a network controller connected between a non-volatile memory and a host with a disturb module connected to the non-volatile memory. A received data write request from a host may prompt the assignment of a first physical block address in the non-volatile memory to a data block of the data write request with the network controller. The data block and first physical block address can each be characterized with the disturb module before the first physical block address is altered to a second block address in the non-volatile memory in response to a disturb strategy generated by the disturb module. The second block address can be selected based on the characterization of the data block and first physical block address with respect to a risk of a disturb condition occurring in the non-volatile memory.

Abstract: An electrical connector can have a switch module connected to a first interface, a second interface, and a third interface with a computing device connected to the first interface, a first peripheral device connected to the second interface, and a second peripheral device connected to the third interface. The first peripheral device may communicate with the computing device via a first conduit that extends through the switch module prior to the switch module activating a second conduit that extends through the switch module in response to detection of an operational condition of the computing device.

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). An initial temperature is stored associated with the programming of data to memory cells in the NVM. A current temperature associated with the NVM is subsequently measured. At such time that a difference interval between the initial and current temperatures exceeds a selected threshold, a preemptive parametric adjustment operation is applied to the NVM. The operation may include a read voltage calibration, a read voltage increment adjustment, and/or a forced garbage collection operation. The operation results in a new set of read voltage set points for the data suitable for the current temperature, and is carried out independently of any pending read commands associated with the data. The initial temperature can be measured during the programming of the data, or measured during the most recent read voltage calibration operation.

Abstract: The present disclosure relates to a data storage device interior components and/or data storage device housing components that include one or more solid-state deposition layers, and related methods of applying solid-state material to said components via solid-state deposition.

Abstract: An apparatus may include a sampling circuit configured to produce a sequence of input samples based on a continuous time input signal and a sample clock signal, the sampling phase of the sequence of input samples based on a phase control value output by a timing recovery circuit. In addition, the apparatus may include the timing recovery circuit configured to receive the sequence of input samples, detect, for a current sample of the sequence of input samples, a phase offset in the sampling phase of the sequence of input samples, the phase offset being a deviation of the sampling phase from an expected phase, and in response to detecting the phase offset, select a bandwidth for timing recovery. Further, the timing recovery circuit may generate an updated phase control value based on the selected bandwidth for timing recovery.

Abstract: Method and apparatus for enhancing power cycle performance of a storage device, such as a solid-state drive (SSD). In some embodiments, map data that describe the contents of a non-volatile memory (NVM) are arranged as snapshots and intervening journal updates. During a scram interval in which the storage device transitions to a powered down condition, the snapshots and journal updates for primary segments with high client interest are updated prior to storage to the NVM. During a reinitialization interval in which the storage device transitions to a powered up condition, the updated primary segments are loaded, after which the storage device provides the client device with an operationally ready notification. Remaining secondary segments are updated and loaded after the notification. The primary segments are identified based on a detected workload from the client device. Configuration changes can further be made based on the detected workload.

Abstract: A data storage system can be vigilant of the acoustic impedance between cooling features and a data storage device to prevent operational degradation in the data storage device as a result of cooling operations from the cooling features. One or more cooling feature may each be positioned on an opposite sides of an air plenum from a data storage device with each cooling feature connected to a cooling module configured to adjust a speed of the first cooling feature in response to a detected operational condition in the data storage device. The cooling features speed adjustment is executed independently to correct an acoustic and vibration disturbance interference in the data storage system.

Abstract: A data storage system can arrange semiconductor memory into a plurality of die sets where performance metrics of execution of a first data access command to a first die set and of a second data access command to a second die set are measured. A proactive strategy is generated to maintain consistent data access command execution performance with a quality of service module based on the measured performance metrics and a third data access command is altered, as directed by the proactive strategy, to prevent a predicted non-uniformity of data access command performance between the first die set and the second die set.

Abstract: Apparatus and method for managing entropy in a cryptographic processing system, such as but not limited to a solid-state drive (SSD). In some embodiments, a processing device is operated to transfer data between a host device and a non-volatile memory (NVM). In response to the detection of a power down event associated with the processing device, entropy associated with the power down event is collected and stored in a memory. Upon a subsequent reinitialization of the processing device, the entropy is conditioned and used as an input to a cryptographic function to subsequently transfer data between the host device and the NVM. In some embodiments, the entropy is obtained from the state of a hardware timer that provides a monotonically increasing count for timing control. In other embodiments, the entropy is obtained from a RAID buffer used to store data to a die set of the NVM.

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.

Abstract: A read channel is configured to obtain an analog readback waveform from a magnetic recording medium of a disk drive at a sampling rate of one sample per one written bit. A buffer is coupled the read channel. Circuitry is configured to inject a plurality of different phase offsets into the read channel for each of a plurality of revolutions of the medium. The circuitry is also configured to store, in a buffer, an amplitude of the readback waveform for each of the different phase offsets. The circuitry is further configured to generate an oversampled readback waveform using the amplitudes stored in the buffer.

Abstract: An apparatus comprises a slider having an air bearing surface (ABS), a leading edge, and a trailing edge opposing the leading edge. A writer having a write pole is situated at or near the ABS. A near-field transducer (NFT) is situated at or near the ABS and between the write pole and the leading edge of the slider. An optical waveguide is configured to couple light from a laser source to the NFT. A contact sensor is situated between the write pole and the trailing edge. The contact sensor comprises a first ABS section situated at or near the ABS, a second ABS section situated at or near the ABS and spaced apart from the first ABS in a cross-track direction by a gap, and a distal section extending away from the ABS and connecting the first ABS section with the second ABS section.

Abstract: A method comprises forming a first structured pattern having a first line width on a substrate. A polymer brush is deposited on the structured pattern, which is annealed a first time at a first temperature and then annealed a second time at a second temperature higher than the first temperature. A block copolymer is deposited on the structured pattern and polymer brush, and aligned first block and second block structures are formed on the structured pattern and polymer brush. The first block structures and portions of the polymer brush and the structured pattern positioned beneath the first block structures are removed, and the substrate between the second block structures is exposed. The second block structures are then removed to form a second structured pattern in the substrate having a second line width, the second line width being smaller than the first line width.

Abstract: A recording head comprises a write pole extending to an air-bearing surface. A near-field transducer is positioned proximate a first side of the write pole in a down-track direction. A heatsink structure is proximate the near-field transducer and positioned between the near-field transducer and the write pole. The heatsink structure extends beyond the near-field transducer in a cross-track direction and extends in a direction normal to the air-bearing surface.